stm32f4xx_dma2d.c 25 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f4xx_dma2d.c
  4. * @author MCD Application Team
  5. * @version V1.8.1
  6. * @date 27-January-2022
  7. * @brief This file provides firmware functions to manage the following
  8. * functionalities of the DMA2D controller (DMA2D) peripheral:
  9. * + Initialization and configuration
  10. * + Interrupts and flags management
  11. *
  12. @verbatim
  13. ===============================================================================
  14. ##### How to use this driver #####
  15. ===============================================================================
  16. [..]
  17. (#) Enable DMA2D clock using
  18. RCC_APB2PeriphResetCmd(RCC_APB2Periph_DMA2D, ENABLE) function.
  19. (#) Configures DMA2D
  20. (++) transfer mode
  21. (++) pixel format, line_number, pixel_per_line
  22. (++) output memory address
  23. (++) alpha value
  24. (++) output offset
  25. (++) Default color (RGB)
  26. (#) Configures Foreground or/and background
  27. (++) memory address
  28. (++) alpha value
  29. (++) offset and default color
  30. (#) Call the DMA2D_Start() to enable the DMA2D controller.
  31. @endverbatim
  32. ******************************************************************************
  33. * @attention
  34. *
  35. * Copyright (c) 2016 STMicroelectronics.
  36. * All rights reserved.
  37. *
  38. * This software is licensed under terms that can be found in the LICENSE file
  39. * in the root directory of this software component.
  40. * If no LICENSE file comes with this software, it is provided AS-IS.
  41. *
  42. ******************************************************************************
  43. */
  44. /* Includes ------------------------------------------------------------------*/
  45. #include "stm32f4xx_dma2d.h"
  46. #include "stm32f4xx_rcc.h"
  47. /** @addtogroup STM32F4xx_StdPeriph_Driver
  48. * @{
  49. */
  50. /** @defgroup DMA2D
  51. * @brief DMA2D driver modules
  52. * @{
  53. */
  54. /* Private typedef -----------------------------------------------------------*/
  55. /* Private define ------------------------------------------------------------*/
  56. /* Private macro -------------------------------------------------------------*/
  57. /* Private variables ---------------------------------------------------------*/
  58. /* Private function prototypes -----------------------------------------------*/
  59. /* Private functions ---------------------------------------------------------*/
  60. #define CR_MASK ((uint32_t)0xFFFCE0FC) /* DMA2D CR Mask */
  61. #define PFCCR_MASK ((uint32_t)0x00FC00C0) /* DMA2D FGPFCCR Mask */
  62. #define DEAD_MASK ((uint32_t)0xFFFF00FE) /* DMA2D DEAD Mask */
  63. /** @defgroup DMA2D_Private_Functions
  64. * @{
  65. */
  66. /** @defgroup DMA2D_Group1 Initialization and Configuration functions
  67. * @brief Initialization and Configuration functions
  68. *
  69. @verbatim
  70. ===============================================================================
  71. ##### Initialization and Configuration functions #####
  72. ===============================================================================
  73. [..] This section provides functions allowing to:
  74. (+) Initialize and configure the DMA2D
  75. (+) Start/Abort/Suspend Transfer
  76. (+) Initialize, configure and set Foreground and background
  77. (+) configure and enable DeadTime
  78. (+) configure lineWatermark
  79. @endverbatim
  80. * @{
  81. */
  82. /**
  83. * @brief Deinitializes the DMA2D peripheral registers to their default reset
  84. * values.
  85. * @param None
  86. * @retval None
  87. */
  88. void DMA2D_DeInit(void)
  89. {
  90. /* Enable DMA2D reset state */
  91. RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2D, ENABLE);
  92. /* Release DMA2D from reset state */
  93. RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2D, DISABLE);
  94. }
  95. /**
  96. * @brief Initializes the DMA2D peripheral according to the specified parameters
  97. * in the DMA2D_InitStruct.
  98. * @note This function can be used only when the DMA2D is disabled.
  99. * @param DMA2D_InitStruct: pointer to a DMA2D_InitTypeDef structure that contains
  100. * the configuration information for the specified DMA2D peripheral.
  101. * @retval None
  102. */
  103. void DMA2D_Init(DMA2D_InitTypeDef* DMA2D_InitStruct)
  104. {
  105. uint32_t outgreen = 0;
  106. uint32_t outred = 0;
  107. uint32_t outalpha = 0;
  108. uint32_t pixline = 0;
  109. /* Check the parameters */
  110. assert_param(IS_DMA2D_MODE(DMA2D_InitStruct->DMA2D_Mode));
  111. assert_param(IS_DMA2D_CMODE(DMA2D_InitStruct->DMA2D_CMode));
  112. assert_param(IS_DMA2D_OGREEN(DMA2D_InitStruct->DMA2D_OutputGreen));
  113. assert_param(IS_DMA2D_ORED(DMA2D_InitStruct->DMA2D_OutputRed));
  114. assert_param(IS_DMA2D_OBLUE(DMA2D_InitStruct->DMA2D_OutputBlue));
  115. assert_param(IS_DMA2D_OALPHA(DMA2D_InitStruct->DMA2D_OutputAlpha));
  116. assert_param(IS_DMA2D_OUTPUT_OFFSET(DMA2D_InitStruct->DMA2D_OutputOffset));
  117. assert_param(IS_DMA2D_LINE(DMA2D_InitStruct->DMA2D_NumberOfLine));
  118. assert_param(IS_DMA2D_PIXEL(DMA2D_InitStruct->DMA2D_PixelPerLine));
  119. /* Configures the DMA2D operation mode */
  120. DMA2D->CR &= (uint32_t)CR_MASK;
  121. DMA2D->CR |= (DMA2D_InitStruct->DMA2D_Mode);
  122. /* Configures the color mode of the output image */
  123. DMA2D->OPFCCR &= ~(uint32_t)DMA2D_OPFCCR_CM;
  124. DMA2D->OPFCCR |= (DMA2D_InitStruct->DMA2D_CMode);
  125. /* Configures the output color */
  126. if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_ARGB8888)
  127. {
  128. outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 8;
  129. outred = DMA2D_InitStruct->DMA2D_OutputRed << 16;
  130. outalpha = DMA2D_InitStruct->DMA2D_OutputAlpha << 24;
  131. }
  132. else
  133. if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_RGB888)
  134. {
  135. outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 8;
  136. outred = DMA2D_InitStruct->DMA2D_OutputRed << 16;
  137. outalpha = (uint32_t)0x00000000;
  138. }
  139. else
  140. if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_RGB565)
  141. {
  142. outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 5;
  143. outred = DMA2D_InitStruct->DMA2D_OutputRed << 11;
  144. outalpha = (uint32_t)0x00000000;
  145. }
  146. else
  147. if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_ARGB1555)
  148. {
  149. outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 5;
  150. outred = DMA2D_InitStruct->DMA2D_OutputRed << 10;
  151. outalpha = DMA2D_InitStruct->DMA2D_OutputAlpha << 15;
  152. }
  153. else /* DMA2D_CMode = DMA2D_ARGB4444 */
  154. {
  155. outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 4;
  156. outred = DMA2D_InitStruct->DMA2D_OutputRed << 8;
  157. outalpha = DMA2D_InitStruct->DMA2D_OutputAlpha << 12;
  158. }
  159. DMA2D->OCOLR = ((outgreen) | (outred) | (DMA2D_InitStruct->DMA2D_OutputBlue) | (outalpha));
  160. /* Configures the output memory address */
  161. DMA2D->OMAR = (DMA2D_InitStruct->DMA2D_OutputMemoryAdd);
  162. /* Configure the line Offset */
  163. DMA2D->OOR &= ~(uint32_t)DMA2D_OOR_LO;
  164. DMA2D->OOR |= (DMA2D_InitStruct->DMA2D_OutputOffset);
  165. /* Configure the number of line and pixel per line */
  166. pixline = DMA2D_InitStruct->DMA2D_PixelPerLine << 16;
  167. DMA2D->NLR &= ~(DMA2D_NLR_NL | DMA2D_NLR_PL);
  168. DMA2D->NLR |= ((DMA2D_InitStruct->DMA2D_NumberOfLine) | (pixline));
  169. /**
  170. * @brief Fills each DMA2D_InitStruct member with its default value.
  171. * @param DMA2D_InitStruct: pointer to a DMA2D_InitTypeDef structure which will
  172. * be initialized.
  173. * @retval None
  174. */
  175. }
  176. void DMA2D_StructInit(DMA2D_InitTypeDef* DMA2D_InitStruct)
  177. {
  178. /* Initialize the transfer mode member */
  179. DMA2D_InitStruct->DMA2D_Mode = DMA2D_M2M;
  180. /* Initialize the output color mode members */
  181. DMA2D_InitStruct->DMA2D_CMode = DMA2D_ARGB8888;
  182. /* Initialize the alpha and RGB values */
  183. DMA2D_InitStruct->DMA2D_OutputGreen = 0x00;
  184. DMA2D_InitStruct->DMA2D_OutputBlue = 0x00;
  185. DMA2D_InitStruct->DMA2D_OutputRed = 0x00;
  186. DMA2D_InitStruct->DMA2D_OutputAlpha = 0x00;
  187. /* Initialize the output memory address */
  188. DMA2D_InitStruct->DMA2D_OutputMemoryAdd = 0x00;
  189. /* Initialize the output offset */
  190. DMA2D_InitStruct->DMA2D_OutputOffset = 0x00;
  191. /* Initialize the number of line and the number of pixel per line */
  192. DMA2D_InitStruct->DMA2D_NumberOfLine = 0x00;
  193. DMA2D_InitStruct->DMA2D_PixelPerLine = 0x00;
  194. }
  195. /**
  196. * @brief Start the DMA2D transfer.
  197. * @param
  198. * @retval None
  199. */
  200. void DMA2D_StartTransfer(void)
  201. {
  202. /* Start DMA2D transfer by setting START bit */
  203. DMA2D->CR |= (uint32_t)DMA2D_CR_START;
  204. }
  205. /**
  206. * @brief Abort the DMA2D transfer.
  207. * @param
  208. * @retval None
  209. */
  210. void DMA2D_AbortTransfer(void)
  211. {
  212. /* Start DMA2D transfer by setting START bit */
  213. DMA2D->CR |= (uint32_t)DMA2D_CR_ABORT;
  214. }
  215. /**
  216. * @brief Stop or continue the DMA2D transfer.
  217. * @param NewState: new state of the DMA2D peripheral.
  218. * This parameter can be: ENABLE or DISABLE.
  219. * @retval None
  220. */
  221. void DMA2D_Suspend(FunctionalState NewState)
  222. {
  223. /* Check the parameters */
  224. assert_param(IS_FUNCTIONAL_STATE(NewState));
  225. if (NewState != DISABLE)
  226. {
  227. /* Suspend DMA2D transfer by setting STOP bit */
  228. DMA2D->CR |= (uint32_t)DMA2D_CR_SUSP;
  229. }
  230. else
  231. {
  232. /* Continue DMA2D transfer by clearing STOP bit */
  233. DMA2D->CR &= ~(uint32_t)DMA2D_CR_SUSP;
  234. }
  235. }
  236. /**
  237. * @brief Configures the Foreground according to the specified parameters
  238. * in the DMA2D_FGStruct.
  239. * @note This function can be used only when the transfer is disabled.
  240. * @param DMA2D_FGStruct: pointer to a DMA2D_FGTypeDef structure that contains
  241. * the configuration information for the specified Background.
  242. * @retval None
  243. */
  244. void DMA2D_FGConfig(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct)
  245. {
  246. uint32_t fg_clutcolormode = 0;
  247. uint32_t fg_clutsize = 0;
  248. uint32_t fg_alpha_mode = 0;
  249. uint32_t fg_alphavalue = 0;
  250. uint32_t fg_colorgreen = 0;
  251. uint32_t fg_colorred = 0;
  252. assert_param(IS_DMA2D_FGO(DMA2D_FG_InitStruct->DMA2D_FGO));
  253. assert_param(IS_DMA2D_FGCM(DMA2D_FG_InitStruct->DMA2D_FGCM));
  254. assert_param(IS_DMA2D_FG_CLUT_CM(DMA2D_FG_InitStruct->DMA2D_FG_CLUT_CM));
  255. assert_param(IS_DMA2D_FG_CLUT_SIZE(DMA2D_FG_InitStruct->DMA2D_FG_CLUT_SIZE));
  256. assert_param(IS_DMA2D_FG_ALPHA_MODE(DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_MODE));
  257. assert_param(IS_DMA2D_FG_ALPHA_VALUE(DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_VALUE));
  258. assert_param(IS_DMA2D_FGC_BLUE(DMA2D_FG_InitStruct->DMA2D_FGC_BLUE));
  259. assert_param(IS_DMA2D_FGC_GREEN(DMA2D_FG_InitStruct->DMA2D_FGC_GREEN));
  260. assert_param(IS_DMA2D_FGC_RED(DMA2D_FG_InitStruct->DMA2D_FGC_RED));
  261. /* Configures the FG memory address */
  262. DMA2D->FGMAR = (DMA2D_FG_InitStruct->DMA2D_FGMA);
  263. /* Configures the FG offset */
  264. DMA2D->FGOR &= ~(uint32_t)DMA2D_FGOR_LO;
  265. DMA2D->FGOR |= (DMA2D_FG_InitStruct->DMA2D_FGO);
  266. /* Configures foreground Pixel Format Convertor */
  267. DMA2D->FGPFCCR &= (uint32_t)PFCCR_MASK;
  268. fg_clutcolormode = DMA2D_FG_InitStruct->DMA2D_FG_CLUT_CM << 4;
  269. fg_clutsize = DMA2D_FG_InitStruct->DMA2D_FG_CLUT_SIZE << 8;
  270. fg_alpha_mode = DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_MODE << 16;
  271. fg_alphavalue = DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_VALUE << 24;
  272. DMA2D->FGPFCCR |= (DMA2D_FG_InitStruct->DMA2D_FGCM | fg_clutcolormode | fg_clutsize | \
  273. fg_alpha_mode | fg_alphavalue);
  274. /* Configures foreground color */
  275. DMA2D->FGCOLR &= ~(DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_RED);
  276. fg_colorgreen = DMA2D_FG_InitStruct->DMA2D_FGC_GREEN << 8;
  277. fg_colorred = DMA2D_FG_InitStruct->DMA2D_FGC_RED << 16;
  278. DMA2D->FGCOLR |= (DMA2D_FG_InitStruct->DMA2D_FGC_BLUE | fg_colorgreen | fg_colorred);
  279. /* Configures foreground CLUT memory address */
  280. DMA2D->FGCMAR = DMA2D_FG_InitStruct->DMA2D_FGCMAR;
  281. }
  282. /**
  283. * @brief Fills each DMA2D_FGStruct member with its default value.
  284. * @param DMA2D_FGStruct: pointer to a DMA2D_FGTypeDef structure which will
  285. * be initialized.
  286. * @retval None
  287. */
  288. void DMA2D_FG_StructInit(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct)
  289. {
  290. /*!< Initialize the DMA2D foreground memory address */
  291. DMA2D_FG_InitStruct->DMA2D_FGMA = 0x00;
  292. /*!< Initialize the DMA2D foreground offset */
  293. DMA2D_FG_InitStruct->DMA2D_FGO = 0x00;
  294. /*!< Initialize the DMA2D foreground color mode */
  295. DMA2D_FG_InitStruct->DMA2D_FGCM = CM_ARGB8888;
  296. /*!< Initialize the DMA2D foreground CLUT color mode */
  297. DMA2D_FG_InitStruct->DMA2D_FG_CLUT_CM = CLUT_CM_ARGB8888;
  298. /*!< Initialize the DMA2D foreground CLUT size */
  299. DMA2D_FG_InitStruct->DMA2D_FG_CLUT_SIZE = 0x00;
  300. /*!< Initialize the DMA2D foreground alpha mode */
  301. DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_MODE = NO_MODIF_ALPHA_VALUE;
  302. /*!< Initialize the DMA2D foreground alpha value */
  303. DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_VALUE = 0x00;
  304. /*!< Initialize the DMA2D foreground blue value */
  305. DMA2D_FG_InitStruct->DMA2D_FGC_BLUE = 0x00;
  306. /*!< Initialize the DMA2D foreground green value */
  307. DMA2D_FG_InitStruct->DMA2D_FGC_GREEN = 0x00;
  308. /*!< Initialize the DMA2D foreground red value */
  309. DMA2D_FG_InitStruct->DMA2D_FGC_RED = 0x00;
  310. /*!< Initialize the DMA2D foreground CLUT memory address */
  311. DMA2D_FG_InitStruct->DMA2D_FGCMAR = 0x00;
  312. }
  313. /**
  314. * @brief Configures the Background according to the specified parameters
  315. * in the DMA2D_BGStruct.
  316. * @note This function can be used only when the transfer is disabled.
  317. * @param DMA2D_BGStruct: pointer to a DMA2D_BGTypeDef structure that contains
  318. * the configuration information for the specified Background.
  319. * @retval None
  320. */
  321. void DMA2D_BGConfig(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct)
  322. {
  323. uint32_t bg_clutcolormode = 0;
  324. uint32_t bg_clutsize = 0;
  325. uint32_t bg_alpha_mode = 0;
  326. uint32_t bg_alphavalue = 0;
  327. uint32_t bg_colorgreen = 0;
  328. uint32_t bg_colorred = 0;
  329. assert_param(IS_DMA2D_BGO(DMA2D_BG_InitStruct->DMA2D_BGO));
  330. assert_param(IS_DMA2D_BGCM(DMA2D_BG_InitStruct->DMA2D_BGCM));
  331. assert_param(IS_DMA2D_BG_CLUT_CM(DMA2D_BG_InitStruct->DMA2D_BG_CLUT_CM));
  332. assert_param(IS_DMA2D_BG_CLUT_SIZE(DMA2D_BG_InitStruct->DMA2D_BG_CLUT_SIZE));
  333. assert_param(IS_DMA2D_BG_ALPHA_MODE(DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_MODE));
  334. assert_param(IS_DMA2D_BG_ALPHA_VALUE(DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_VALUE));
  335. assert_param(IS_DMA2D_BGC_BLUE(DMA2D_BG_InitStruct->DMA2D_BGC_BLUE));
  336. assert_param(IS_DMA2D_BGC_GREEN(DMA2D_BG_InitStruct->DMA2D_BGC_GREEN));
  337. assert_param(IS_DMA2D_BGC_RED(DMA2D_BG_InitStruct->DMA2D_BGC_RED));
  338. /* Configures the BG memory address */
  339. DMA2D->BGMAR = (DMA2D_BG_InitStruct->DMA2D_BGMA);
  340. /* Configures the BG offset */
  341. DMA2D->BGOR &= ~(uint32_t)DMA2D_BGOR_LO;
  342. DMA2D->BGOR |= (DMA2D_BG_InitStruct->DMA2D_BGO);
  343. /* Configures background Pixel Format Convertor */
  344. DMA2D->BGPFCCR &= (uint32_t)PFCCR_MASK;
  345. bg_clutcolormode = DMA2D_BG_InitStruct->DMA2D_BG_CLUT_CM << 4;
  346. bg_clutsize = DMA2D_BG_InitStruct->DMA2D_BG_CLUT_SIZE << 8;
  347. bg_alpha_mode = DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_MODE << 16;
  348. bg_alphavalue = DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_VALUE << 24;
  349. DMA2D->BGPFCCR |= (DMA2D_BG_InitStruct->DMA2D_BGCM | bg_clutcolormode | bg_clutsize | \
  350. bg_alpha_mode | bg_alphavalue);
  351. /* Configures background color */
  352. DMA2D->BGCOLR &= ~(DMA2D_BGCOLR_BLUE | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_RED);
  353. bg_colorgreen = DMA2D_BG_InitStruct->DMA2D_BGC_GREEN << 8;
  354. bg_colorred = DMA2D_BG_InitStruct->DMA2D_BGC_RED << 16;
  355. DMA2D->BGCOLR |= (DMA2D_BG_InitStruct->DMA2D_BGC_BLUE | bg_colorgreen | bg_colorred);
  356. /* Configures background CLUT memory address */
  357. DMA2D->BGCMAR = DMA2D_BG_InitStruct->DMA2D_BGCMAR;
  358. }
  359. /**
  360. * @brief Fills each DMA2D_BGStruct member with its default value.
  361. * @param DMA2D_BGStruct: pointer to a DMA2D_BGTypeDef structure which will
  362. * be initialized.
  363. * @retval None
  364. */
  365. void DMA2D_BG_StructInit(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct)
  366. {
  367. /*!< Initialize the DMA2D background memory address */
  368. DMA2D_BG_InitStruct->DMA2D_BGMA = 0x00;
  369. /*!< Initialize the DMA2D background offset */
  370. DMA2D_BG_InitStruct->DMA2D_BGO = 0x00;
  371. /*!< Initialize the DMA2D background color mode */
  372. DMA2D_BG_InitStruct->DMA2D_BGCM = CM_ARGB8888;
  373. /*!< Initialize the DMA2D background CLUT color mode */
  374. DMA2D_BG_InitStruct->DMA2D_BG_CLUT_CM = CLUT_CM_ARGB8888;
  375. /*!< Initialize the DMA2D background CLUT size */
  376. DMA2D_BG_InitStruct->DMA2D_BG_CLUT_SIZE = 0x00;
  377. /*!< Initialize the DMA2D background alpha mode */
  378. DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_MODE = NO_MODIF_ALPHA_VALUE;
  379. /*!< Initialize the DMA2D background alpha value */
  380. DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_VALUE = 0x00;
  381. /*!< Initialize the DMA2D background blue value */
  382. DMA2D_BG_InitStruct->DMA2D_BGC_BLUE = 0x00;
  383. /*!< Initialize the DMA2D background green value */
  384. DMA2D_BG_InitStruct->DMA2D_BGC_GREEN = 0x00;
  385. /*!< Initialize the DMA2D background red value */
  386. DMA2D_BG_InitStruct->DMA2D_BGC_RED = 0x00;
  387. /*!< Initialize the DMA2D background CLUT memory address */
  388. DMA2D_BG_InitStruct->DMA2D_BGCMAR = 0x00;
  389. }
  390. /**
  391. * @brief Start the automatic loading of the CLUT or abort the transfer.
  392. * @param NewState: new state of the DMA2D peripheral.
  393. * This parameter can be: ENABLE or DISABLE.
  394. * @retval None
  395. */
  396. void DMA2D_FGStart(FunctionalState NewState)
  397. {
  398. /* Check the parameters */
  399. assert_param(IS_FUNCTIONAL_STATE(NewState));
  400. if (NewState != DISABLE)
  401. {
  402. /* Start the automatic loading of the CLUT */
  403. DMA2D->FGPFCCR |= DMA2D_FGPFCCR_START;
  404. }
  405. else
  406. {
  407. /* abort the transfer */
  408. DMA2D->FGPFCCR &= (uint32_t)~DMA2D_FGPFCCR_START;
  409. }
  410. }
  411. /**
  412. * @brief Start the automatic loading of the CLUT or abort the transfer.
  413. * @param NewState: new state of the DMA2D peripheral.
  414. * This parameter can be: ENABLE or DISABLE.
  415. * @retval None
  416. */
  417. void DMA2D_BGStart(FunctionalState NewState)
  418. {
  419. /* Check the parameters */
  420. assert_param(IS_FUNCTIONAL_STATE(NewState));
  421. if (NewState != DISABLE)
  422. {
  423. /* Start the automatic loading of the CLUT */
  424. DMA2D->BGPFCCR |= DMA2D_BGPFCCR_START;
  425. }
  426. else
  427. {
  428. /* abort the transfer */
  429. DMA2D->BGPFCCR &= (uint32_t)~DMA2D_BGPFCCR_START;
  430. }
  431. }
  432. /**
  433. * @brief Configures the DMA2D dead time.
  434. * @param DMA2D_DeadTime: specifies the DMA2D dead time.
  435. * This parameter can be one of the following values:
  436. * @retval None
  437. */
  438. void DMA2D_DeadTimeConfig(uint32_t DMA2D_DeadTime, FunctionalState NewState)
  439. {
  440. uint32_t DeadTime;
  441. /* Check the parameters */
  442. assert_param(IS_DMA2D_DEAD_TIME(DMA2D_DeadTime));
  443. assert_param(IS_FUNCTIONAL_STATE(NewState));
  444. if (NewState != DISABLE)
  445. {
  446. /* Enable and Configures the dead time */
  447. DMA2D->AMTCR &= (uint32_t)DEAD_MASK;
  448. DeadTime = DMA2D_DeadTime << 8;
  449. DMA2D->AMTCR |= (DeadTime | DMA2D_AMTCR_EN);
  450. }
  451. else
  452. {
  453. DMA2D->AMTCR &= ~(uint32_t)DMA2D_AMTCR_EN;
  454. }
  455. }
  456. /**
  457. * @brief Define the configuration of the line watermark .
  458. * @param DMA2D_LWatermarkConfig: Line Watermark configuration.
  459. * @retval None
  460. */
  461. void DMA2D_LineWatermarkConfig(uint32_t DMA2D_LWatermarkConfig)
  462. {
  463. /* Check the parameters */
  464. assert_param(IS_DMA2D_LineWatermark(DMA2D_LWatermarkConfig));
  465. /* Sets the Line watermark configuration */
  466. DMA2D->LWR = (uint32_t)DMA2D_LWatermarkConfig;
  467. }
  468. /**
  469. * @}
  470. */
  471. /** @defgroup DMA2D_Group2 Interrupts and flags management functions
  472. * @brief Interrupts and flags management functions
  473. *
  474. @verbatim
  475. ===============================================================================
  476. ##### Interrupts and flags management functions #####
  477. ===============================================================================
  478. [..] This section provides functions allowing to configure the DMA2D
  479. Interrupts and to get the status and clear flags and Interrupts
  480. pending bits.
  481. [..] The DMA2D provides 6 Interrupts sources and 6 Flags
  482. *** Flags ***
  483. =============
  484. [..]
  485. (+) DMA2D_FLAG_CE : Configuration Error Interrupt flag
  486. (+) DMA2D_FLAG_CAE: CLUT Access Error Interrupt flag
  487. (+) DMA2D_FLAG_TW: Transfer Watermark Interrupt flag
  488. (+) DMA2D_FLAG_TC: Transfer Complete interrupt flag
  489. (+) DMA2D_FLAG_TE: Transfer Error interrupt flag
  490. (+) DMA2D_FLAG_CTC: CLUT Transfer Complete Interrupt flag
  491. *** Interrupts ***
  492. ==================
  493. [..]
  494. (+) DMA2D_IT_CE: Configuration Error Interrupt is generated when a wrong
  495. configuration is detected
  496. (+) DMA2D_IT_CAE: CLUT Access Error Interrupt
  497. (+) DMA2D_IT_TW: Transfer Watermark Interrupt is generated when
  498. the programmed watermark is reached
  499. (+) DMA2D_IT_TE: Transfer Error interrupt is generated when the CPU trying
  500. to access the CLUT while a CLUT loading or a DMA2D1 transfer
  501. is on going
  502. (+) DMA2D_IT_CTC: CLUT Transfer Complete Interrupt
  503. (+) DMA2D_IT_TC: Transfer Complete interrupt
  504. @endverbatim
  505. * @{
  506. */
  507. /**
  508. * @brief Enables or disables the specified DMA2D's interrupts.
  509. * @param DMA2D_IT: specifies the DMA2D interrupts sources to be enabled or disabled.
  510. * This parameter can be any combination of the following values:
  511. * @arg DMA2D_IT_CE: Configuration Error Interrupt Enable.
  512. * @arg DMA2D_IT_CTC: CLUT Transfer Complete Interrupt Enable.
  513. * @arg DMA2D_IT_CAE: CLUT Access Error Interrupt Enable.
  514. * @arg DMA2D_IT_TW: Transfer Watermark Interrupt Enable.
  515. * @arg DMA2D_IT_TC: Transfer Complete interrupt enable.
  516. * @arg DMA2D_IT_TE: Transfer Error interrupt enable.
  517. * @param NewState: new state of the specified DMA2D interrupts.
  518. * This parameter can be: ENABLE or DISABLE.
  519. * @retval None
  520. */
  521. void DMA2D_ITConfig(uint32_t DMA2D_IT, FunctionalState NewState)
  522. {
  523. /* Check the parameters */
  524. assert_param(IS_DMA2D_IT(DMA2D_IT));
  525. assert_param(IS_FUNCTIONAL_STATE(NewState));
  526. if (NewState != DISABLE)
  527. {
  528. /* Enable the selected DMA2D interrupts */
  529. DMA2D->CR |= DMA2D_IT;
  530. }
  531. else
  532. {
  533. /* Disable the selected DMA2D interrupts */
  534. DMA2D->CR &= (uint32_t)~DMA2D_IT;
  535. }
  536. }
  537. /**
  538. * @brief Checks whether the specified DMA2D's flag is set or not.
  539. * @param DMA2D_FLAG: specifies the flag to check.
  540. * This parameter can be one of the following values:
  541. * @arg DMA2D_FLAG_CE: Configuration Error Interrupt flag.
  542. * @arg DMA2D_FLAG_CTC: CLUT Transfer Complete Interrupt flag.
  543. * @arg DMA2D_FLAG_CAE: CLUT Access Error Interrupt flag.
  544. * @arg DMA2D_FLAG_TW: Transfer Watermark Interrupt flag.
  545. * @arg DMA2D_FLAG_TC: Transfer Complete interrupt flag.
  546. * @arg DMA2D_FLAG_TE: Transfer Error interrupt flag.
  547. * @retval The new state of DMA2D_FLAG (SET or RESET).
  548. */
  549. FlagStatus DMA2D_GetFlagStatus(uint32_t DMA2D_FLAG)
  550. {
  551. FlagStatus bitstatus = RESET;
  552. /* Check the parameters */
  553. assert_param(IS_DMA2D_GET_FLAG(DMA2D_FLAG));
  554. /* Check the status of the specified DMA2D flag */
  555. if (((DMA2D->ISR) & DMA2D_FLAG) != (uint32_t)RESET)
  556. {
  557. /* DMA2D_FLAG is set */
  558. bitstatus = SET;
  559. }
  560. else
  561. {
  562. /* DMA2D_FLAG is reset */
  563. bitstatus = RESET;
  564. }
  565. /* Return the DMA2D_FLAG status */
  566. return bitstatus;
  567. }
  568. /**
  569. * @brief Clears the DMA2D's pending flags.
  570. * @param DMA2D_FLAG: specifies the flag to clear.
  571. * This parameter can be any combination of the following values:
  572. * @arg DMA2D_FLAG_CE: Configuration Error Interrupt flag.
  573. * @arg DMA2D_FLAG_CTC: CLUT Transfer Complete Interrupt flag.
  574. * @arg DMA2D_FLAG_CAE: CLUT Access Error Interrupt flag.
  575. * @arg DMA2D_FLAG_TW: Transfer Watermark Interrupt flag.
  576. * @arg DMA2D_FLAG_TC: Transfer Complete interrupt flag.
  577. * @arg DMA2D_FLAG_TE: Transfer Error interrupt flag.
  578. * @retval None
  579. */
  580. void DMA2D_ClearFlag(uint32_t DMA2D_FLAG)
  581. {
  582. /* Check the parameters */
  583. assert_param(IS_DMA2D_GET_FLAG(DMA2D_FLAG));
  584. /* Clear the corresponding DMA2D flag */
  585. DMA2D->IFCR = (uint32_t)DMA2D_FLAG;
  586. }
  587. /**
  588. * @brief Checks whether the specified DMA2D's interrupt has occurred or not.
  589. * @param DMA2D_IT: specifies the DMA2D interrupts sources to check.
  590. * This parameter can be one of the following values:
  591. * @arg DMA2D_IT_CE: Configuration Error Interrupt Enable.
  592. * @arg DMA2D_IT_CTC: CLUT Transfer Complete Interrupt Enable.
  593. * @arg DMA2D_IT_CAE: CLUT Access Error Interrupt Enable.
  594. * @arg DMA2D_IT_TW: Transfer Watermark Interrupt Enable.
  595. * @arg DMA2D_IT_TC: Transfer Complete interrupt enable.
  596. * @arg DMA2D_IT_TE: Transfer Error interrupt enable.
  597. * @retval The new state of the DMA2D_IT (SET or RESET).
  598. */
  599. ITStatus DMA2D_GetITStatus(uint32_t DMA2D_IT)
  600. {
  601. ITStatus bitstatus = RESET;
  602. uint32_t DMA2D_IT_FLAG = DMA2D_IT >> 8;
  603. /* Check the parameters */
  604. assert_param(IS_DMA2D_IT(DMA2D_IT));
  605. if ((DMA2D->ISR & DMA2D_IT_FLAG) != (uint32_t)RESET)
  606. {
  607. bitstatus = SET;
  608. }
  609. else
  610. {
  611. bitstatus = RESET;
  612. }
  613. if (((DMA2D->CR & DMA2D_IT) != (uint32_t)RESET) && (bitstatus != (uint32_t)RESET))
  614. {
  615. bitstatus = SET;
  616. }
  617. else
  618. {
  619. bitstatus = RESET;
  620. }
  621. return bitstatus;
  622. }
  623. /**
  624. * @brief Clears the DMA2D's interrupt pending bits.
  625. * @param DMA2D_IT: specifies the interrupt pending bit to clear.
  626. * This parameter can be any combination of the following values:
  627. * @arg DMA2D_IT_CE: Configuration Error Interrupt.
  628. * @arg DMA2D_IT_CTC: CLUT Transfer Complete Interrupt.
  629. * @arg DMA2D_IT_CAE: CLUT Access Error Interrupt.
  630. * @arg DMA2D_IT_TW: Transfer Watermark Interrupt.
  631. * @arg DMA2D_IT_TC: Transfer Complete interrupt.
  632. * @arg DMA2D_IT_TE: Transfer Error interrupt.
  633. * @retval None
  634. */
  635. void DMA2D_ClearITPendingBit(uint32_t DMA2D_IT)
  636. {
  637. /* Check the parameters */
  638. assert_param(IS_DMA2D_IT(DMA2D_IT));
  639. DMA2D_IT = DMA2D_IT >> 8;
  640. /* Clear the corresponding DMA2D Interrupt */
  641. DMA2D->IFCR = (uint32_t)DMA2D_IT;
  642. }
  643. /**
  644. * @}
  645. */
  646. /**
  647. * @}
  648. */
  649. /**
  650. * @}
  651. */
  652. /**
  653. * @}
  654. */