stm32f4xx_cryp_aes.c 55 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f4xx_cryp_aes.c
  4. * @author MCD Application Team
  5. * @version V1.8.1
  6. * @date 27-January-2022
  7. * @brief This file provides high level functions to encrypt and decrypt an
  8. * input message using AES in ECB/CBC/CTR/GCM/CCM modes.
  9. * It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP
  10. * peripheral.
  11. * AES-ECB/CBC/CTR/GCM/CCM modes are available on STM32F437x Devices.
  12. * For STM32F41xx Devices, only AES-ECB/CBC/CTR modes are available.
  13. *
  14. @verbatim
  15. ===================================================================
  16. ##### How to use this driver #####
  17. ===================================================================
  18. [..]
  19. (#) Enable The CRYP controller clock using
  20. RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
  21. (#) Encrypt and decrypt using AES in ECB Mode using CRYP_AES_ECB() function.
  22. (#) Encrypt and decrypt using AES in CBC Mode using CRYP_AES_CBC() function.
  23. (#) Encrypt and decrypt using AES in CTR Mode using CRYP_AES_CTR() function.
  24. (#) Encrypt and decrypt using AES in GCM Mode using CRYP_AES_GCM() function.
  25. (#) Encrypt and decrypt using AES in CCM Mode using CRYP_AES_CCM() function.
  26. @endverbatim
  27. *
  28. ******************************************************************************
  29. * @attention
  30. *
  31. * Copyright (c) 2016 STMicroelectronics.
  32. * All rights reserved.
  33. *
  34. * This software is licensed under terms that can be found in the LICENSE file
  35. * in the root directory of this software component.
  36. * If no LICENSE file comes with this software, it is provided AS-IS.
  37. *
  38. ******************************************************************************
  39. */
  40. /* Includes ------------------------------------------------------------------*/
  41. #include "stm32f4xx_cryp.h"
  42. /** @addtogroup STM32F4xx_StdPeriph_Driver
  43. * @{
  44. */
  45. /** @defgroup CRYP
  46. * @brief CRYP driver modules
  47. * @{
  48. */
  49. /* Private typedef -----------------------------------------------------------*/
  50. /* Private define ------------------------------------------------------------*/
  51. #define AESBUSY_TIMEOUT ((uint32_t) 0x00010000)
  52. /* Private macro -------------------------------------------------------------*/
  53. /* Private variables ---------------------------------------------------------*/
  54. /* Private function prototypes -----------------------------------------------*/
  55. /* Private functions ---------------------------------------------------------*/
  56. /** @defgroup CRYP_Private_Functions
  57. * @{
  58. */
  59. /** @defgroup CRYP_Group6 High Level AES functions
  60. * @brief High Level AES functions
  61. *
  62. @verbatim
  63. ===============================================================================
  64. ##### High Level AES functions #####
  65. ===============================================================================
  66. @endverbatim
  67. * @{
  68. */
  69. /**
  70. * @brief Encrypt and decrypt using AES in ECB Mode
  71. * @param Mode: encryption or decryption Mode.
  72. * This parameter can be one of the following values:
  73. * @arg MODE_ENCRYPT: Encryption
  74. * @arg MODE_DECRYPT: Decryption
  75. * @param Key: Key used for AES algorithm.
  76. * @param Keysize: length of the Key, must be a 128, 192 or 256.
  77. * @param Input: pointer to the Input buffer.
  78. * @param Ilength: length of the Input buffer, must be a multiple of 16.
  79. * @param Output: pointer to the returned buffer.
  80. * @retval An ErrorStatus enumeration value:
  81. * - SUCCESS: Operation done
  82. * - ERROR: Operation failed
  83. */
  84. ErrorStatus CRYP_AES_ECB(uint8_t Mode, uint8_t* Key, uint16_t Keysize,
  85. uint8_t* Input, uint32_t Ilength, uint8_t* Output)
  86. {
  87. CRYP_InitTypeDef AES_CRYP_InitStructure;
  88. CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure;
  89. __IO uint32_t counter = 0;
  90. uint32_t busystatus = 0;
  91. ErrorStatus status = SUCCESS;
  92. uint32_t keyaddr = (uint32_t)Key;
  93. uint32_t inputaddr = (uint32_t)Input;
  94. uint32_t outputaddr = (uint32_t)Output;
  95. uint32_t i = 0;
  96. /* Crypto structures initialisation*/
  97. CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure);
  98. switch(Keysize)
  99. {
  100. case 128:
  101. AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b;
  102. AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
  103. keyaddr+=4;
  104. AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
  105. keyaddr+=4;
  106. AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
  107. keyaddr+=4;
  108. AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
  109. break;
  110. case 192:
  111. AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b;
  112. AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
  113. keyaddr+=4;
  114. AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
  115. keyaddr+=4;
  116. AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
  117. keyaddr+=4;
  118. AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
  119. keyaddr+=4;
  120. AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
  121. keyaddr+=4;
  122. AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
  123. break;
  124. case 256:
  125. AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b;
  126. AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr));
  127. keyaddr+=4;
  128. AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr));
  129. keyaddr+=4;
  130. AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
  131. keyaddr+=4;
  132. AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
  133. keyaddr+=4;
  134. AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
  135. keyaddr+=4;
  136. AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
  137. keyaddr+=4;
  138. AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
  139. keyaddr+=4;
  140. AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
  141. break;
  142. default:
  143. break;
  144. }
  145. /*------------------ AES Decryption ------------------*/
  146. if(Mode == MODE_DECRYPT) /* AES decryption */
  147. {
  148. /* Flush IN/OUT FIFOs */
  149. CRYP_FIFOFlush();
  150. /* Crypto Init for Key preparation for decryption process */
  151. AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
  152. AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_Key;
  153. AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_32b;
  154. CRYP_Init(&AES_CRYP_InitStructure);
  155. /* Key Initialisation */
  156. CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
  157. /* Enable Crypto processor */
  158. CRYP_Cmd(ENABLE);
  159. /* wait until the Busy flag is RESET */
  160. do
  161. {
  162. busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
  163. counter++;
  164. }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
  165. if (busystatus != RESET)
  166. {
  167. status = ERROR;
  168. }
  169. else
  170. {
  171. /* Crypto Init for decryption process */
  172. AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
  173. }
  174. }
  175. /*------------------ AES Encryption ------------------*/
  176. else /* AES encryption */
  177. {
  178. CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
  179. /* Crypto Init for Encryption process */
  180. AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
  181. }
  182. AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_ECB;
  183. AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
  184. CRYP_Init(&AES_CRYP_InitStructure);
  185. /* Flush IN/OUT FIFOs */
  186. CRYP_FIFOFlush();
  187. /* Enable Crypto processor */
  188. CRYP_Cmd(ENABLE);
  189. if(CRYP_GetCmdStatus() == DISABLE)
  190. {
  191. /* The CRYP peripheral clock is not enabled or the device doesn't embed
  192. the CRYP peripheral (please check the device sales type. */
  193. return(ERROR);
  194. }
  195. for(i=0; ((i<Ilength) && (status != ERROR)); i+=16)
  196. {
  197. /* Write the Input block in the IN FIFO */
  198. CRYP_DataIn(*(uint32_t*)(inputaddr));
  199. inputaddr+=4;
  200. CRYP_DataIn(*(uint32_t*)(inputaddr));
  201. inputaddr+=4;
  202. CRYP_DataIn(*(uint32_t*)(inputaddr));
  203. inputaddr+=4;
  204. CRYP_DataIn(*(uint32_t*)(inputaddr));
  205. inputaddr+=4;
  206. /* Wait until the complete message has been processed */
  207. counter = 0;
  208. do
  209. {
  210. busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
  211. counter++;
  212. }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
  213. if (busystatus != RESET)
  214. {
  215. status = ERROR;
  216. }
  217. else
  218. {
  219. /* Read the Output block from the Output FIFO */
  220. *(uint32_t*)(outputaddr) = CRYP_DataOut();
  221. outputaddr+=4;
  222. *(uint32_t*)(outputaddr) = CRYP_DataOut();
  223. outputaddr+=4;
  224. *(uint32_t*)(outputaddr) = CRYP_DataOut();
  225. outputaddr+=4;
  226. *(uint32_t*)(outputaddr) = CRYP_DataOut();
  227. outputaddr+=4;
  228. }
  229. }
  230. /* Disable Crypto */
  231. CRYP_Cmd(DISABLE);
  232. return status;
  233. }
  234. /**
  235. * @brief Encrypt and decrypt using AES in CBC Mode
  236. * @param Mode: encryption or decryption Mode.
  237. * This parameter can be one of the following values:
  238. * @arg MODE_ENCRYPT: Encryption
  239. * @arg MODE_DECRYPT: Decryption
  240. * @param InitVectors: Initialisation Vectors used for AES algorithm.
  241. * @param Key: Key used for AES algorithm.
  242. * @param Keysize: length of the Key, must be a 128, 192 or 256.
  243. * @param Input: pointer to the Input buffer.
  244. * @param Ilength: length of the Input buffer, must be a multiple of 16.
  245. * @param Output: pointer to the returned buffer.
  246. * @retval An ErrorStatus enumeration value:
  247. * - SUCCESS: Operation done
  248. * - ERROR: Operation failed
  249. */
  250. ErrorStatus CRYP_AES_CBC(uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key,
  251. uint16_t Keysize, uint8_t *Input, uint32_t Ilength,
  252. uint8_t *Output)
  253. {
  254. CRYP_InitTypeDef AES_CRYP_InitStructure;
  255. CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure;
  256. CRYP_IVInitTypeDef AES_CRYP_IVInitStructure;
  257. __IO uint32_t counter = 0;
  258. uint32_t busystatus = 0;
  259. ErrorStatus status = SUCCESS;
  260. uint32_t keyaddr = (uint32_t)Key;
  261. uint32_t inputaddr = (uint32_t)Input;
  262. uint32_t outputaddr = (uint32_t)Output;
  263. uint32_t ivaddr = (uint32_t)InitVectors;
  264. uint32_t i = 0;
  265. /* Crypto structures initialisation*/
  266. CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure);
  267. switch(Keysize)
  268. {
  269. case 128:
  270. AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b;
  271. AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
  272. keyaddr+=4;
  273. AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
  274. keyaddr+=4;
  275. AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
  276. keyaddr+=4;
  277. AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
  278. break;
  279. case 192:
  280. AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b;
  281. AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
  282. keyaddr+=4;
  283. AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
  284. keyaddr+=4;
  285. AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
  286. keyaddr+=4;
  287. AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
  288. keyaddr+=4;
  289. AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
  290. keyaddr+=4;
  291. AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
  292. break;
  293. case 256:
  294. AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b;
  295. AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr));
  296. keyaddr+=4;
  297. AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr));
  298. keyaddr+=4;
  299. AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
  300. keyaddr+=4;
  301. AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
  302. keyaddr+=4;
  303. AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
  304. keyaddr+=4;
  305. AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
  306. keyaddr+=4;
  307. AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
  308. keyaddr+=4;
  309. AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
  310. break;
  311. default:
  312. break;
  313. }
  314. /* CRYP Initialization Vectors */
  315. AES_CRYP_IVInitStructure.CRYP_IV0Left = __REV(*(uint32_t*)(ivaddr));
  316. ivaddr+=4;
  317. AES_CRYP_IVInitStructure.CRYP_IV0Right= __REV(*(uint32_t*)(ivaddr));
  318. ivaddr+=4;
  319. AES_CRYP_IVInitStructure.CRYP_IV1Left = __REV(*(uint32_t*)(ivaddr));
  320. ivaddr+=4;
  321. AES_CRYP_IVInitStructure.CRYP_IV1Right= __REV(*(uint32_t*)(ivaddr));
  322. /*------------------ AES Decryption ------------------*/
  323. if(Mode == MODE_DECRYPT) /* AES decryption */
  324. {
  325. /* Flush IN/OUT FIFOs */
  326. CRYP_FIFOFlush();
  327. /* Crypto Init for Key preparation for decryption process */
  328. AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
  329. AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_Key;
  330. AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_32b;
  331. CRYP_Init(&AES_CRYP_InitStructure);
  332. /* Key Initialisation */
  333. CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
  334. /* Enable Crypto processor */
  335. CRYP_Cmd(ENABLE);
  336. /* wait until the Busy flag is RESET */
  337. do
  338. {
  339. busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
  340. counter++;
  341. }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
  342. if (busystatus != RESET)
  343. {
  344. status = ERROR;
  345. }
  346. else
  347. {
  348. /* Crypto Init for decryption process */
  349. AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
  350. }
  351. }
  352. /*------------------ AES Encryption ------------------*/
  353. else /* AES encryption */
  354. {
  355. CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
  356. /* Crypto Init for Encryption process */
  357. AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
  358. }
  359. AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_CBC;
  360. AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
  361. CRYP_Init(&AES_CRYP_InitStructure);
  362. /* CRYP Initialization Vectors */
  363. CRYP_IVInit(&AES_CRYP_IVInitStructure);
  364. /* Flush IN/OUT FIFOs */
  365. CRYP_FIFOFlush();
  366. /* Enable Crypto processor */
  367. CRYP_Cmd(ENABLE);
  368. if(CRYP_GetCmdStatus() == DISABLE)
  369. {
  370. /* The CRYP peripheral clock is not enabled or the device doesn't embed
  371. the CRYP peripheral (please check the device sales type. */
  372. return(ERROR);
  373. }
  374. for(i=0; ((i<Ilength) && (status != ERROR)); i+=16)
  375. {
  376. /* Write the Input block in the IN FIFO */
  377. CRYP_DataIn(*(uint32_t*)(inputaddr));
  378. inputaddr+=4;
  379. CRYP_DataIn(*(uint32_t*)(inputaddr));
  380. inputaddr+=4;
  381. CRYP_DataIn(*(uint32_t*)(inputaddr));
  382. inputaddr+=4;
  383. CRYP_DataIn(*(uint32_t*)(inputaddr));
  384. inputaddr+=4;
  385. /* Wait until the complete message has been processed */
  386. counter = 0;
  387. do
  388. {
  389. busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
  390. counter++;
  391. }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
  392. if (busystatus != RESET)
  393. {
  394. status = ERROR;
  395. }
  396. else
  397. {
  398. /* Read the Output block from the Output FIFO */
  399. *(uint32_t*)(outputaddr) = CRYP_DataOut();
  400. outputaddr+=4;
  401. *(uint32_t*)(outputaddr) = CRYP_DataOut();
  402. outputaddr+=4;
  403. *(uint32_t*)(outputaddr) = CRYP_DataOut();
  404. outputaddr+=4;
  405. *(uint32_t*)(outputaddr) = CRYP_DataOut();
  406. outputaddr+=4;
  407. }
  408. }
  409. /* Disable Crypto */
  410. CRYP_Cmd(DISABLE);
  411. return status;
  412. }
  413. /**
  414. * @brief Encrypt and decrypt using AES in CTR Mode
  415. * @param Mode: encryption or decryption Mode.
  416. * This parameter can be one of the following values:
  417. * @arg MODE_ENCRYPT: Encryption
  418. * @arg MODE_DECRYPT: Decryption
  419. * @param InitVectors: Initialisation Vectors used for AES algorithm.
  420. * @param Key: Key used for AES algorithm.
  421. * @param Keysize: length of the Key, must be a 128, 192 or 256.
  422. * @param Input: pointer to the Input buffer.
  423. * @param Ilength: length of the Input buffer, must be a multiple of 16.
  424. * @param Output: pointer to the returned buffer.
  425. * @retval An ErrorStatus enumeration value:
  426. * - SUCCESS: Operation done
  427. * - ERROR: Operation failed
  428. */
  429. ErrorStatus CRYP_AES_CTR(uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key,
  430. uint16_t Keysize, uint8_t *Input, uint32_t Ilength,
  431. uint8_t *Output)
  432. {
  433. CRYP_InitTypeDef AES_CRYP_InitStructure;
  434. CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure;
  435. CRYP_IVInitTypeDef AES_CRYP_IVInitStructure;
  436. __IO uint32_t counter = 0;
  437. uint32_t busystatus = 0;
  438. ErrorStatus status = SUCCESS;
  439. uint32_t keyaddr = (uint32_t)Key;
  440. uint32_t inputaddr = (uint32_t)Input;
  441. uint32_t outputaddr = (uint32_t)Output;
  442. uint32_t ivaddr = (uint32_t)InitVectors;
  443. uint32_t i = 0;
  444. /* Crypto structures initialisation*/
  445. CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure);
  446. switch(Keysize)
  447. {
  448. case 128:
  449. AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b;
  450. AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
  451. keyaddr+=4;
  452. AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
  453. keyaddr+=4;
  454. AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
  455. keyaddr+=4;
  456. AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
  457. break;
  458. case 192:
  459. AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b;
  460. AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
  461. keyaddr+=4;
  462. AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
  463. keyaddr+=4;
  464. AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
  465. keyaddr+=4;
  466. AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
  467. keyaddr+=4;
  468. AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
  469. keyaddr+=4;
  470. AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
  471. break;
  472. case 256:
  473. AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b;
  474. AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr));
  475. keyaddr+=4;
  476. AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr));
  477. keyaddr+=4;
  478. AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
  479. keyaddr+=4;
  480. AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
  481. keyaddr+=4;
  482. AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
  483. keyaddr+=4;
  484. AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
  485. keyaddr+=4;
  486. AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
  487. keyaddr+=4;
  488. AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
  489. break;
  490. default:
  491. break;
  492. }
  493. /* CRYP Initialization Vectors */
  494. AES_CRYP_IVInitStructure.CRYP_IV0Left = __REV(*(uint32_t*)(ivaddr));
  495. ivaddr+=4;
  496. AES_CRYP_IVInitStructure.CRYP_IV0Right= __REV(*(uint32_t*)(ivaddr));
  497. ivaddr+=4;
  498. AES_CRYP_IVInitStructure.CRYP_IV1Left = __REV(*(uint32_t*)(ivaddr));
  499. ivaddr+=4;
  500. AES_CRYP_IVInitStructure.CRYP_IV1Right= __REV(*(uint32_t*)(ivaddr));
  501. /* Key Initialisation */
  502. CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
  503. /*------------------ AES Decryption ------------------*/
  504. if(Mode == MODE_DECRYPT) /* AES decryption */
  505. {
  506. /* Crypto Init for decryption process */
  507. AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
  508. }
  509. /*------------------ AES Encryption ------------------*/
  510. else /* AES encryption */
  511. {
  512. /* Crypto Init for Encryption process */
  513. AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
  514. }
  515. AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_CTR;
  516. AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
  517. CRYP_Init(&AES_CRYP_InitStructure);
  518. /* CRYP Initialization Vectors */
  519. CRYP_IVInit(&AES_CRYP_IVInitStructure);
  520. /* Flush IN/OUT FIFOs */
  521. CRYP_FIFOFlush();
  522. /* Enable Crypto processor */
  523. CRYP_Cmd(ENABLE);
  524. if(CRYP_GetCmdStatus() == DISABLE)
  525. {
  526. /* The CRYP peripheral clock is not enabled or the device doesn't embed
  527. the CRYP peripheral (please check the device sales type. */
  528. return(ERROR);
  529. }
  530. for(i=0; ((i<Ilength) && (status != ERROR)); i+=16)
  531. {
  532. /* Write the Input block in the IN FIFO */
  533. CRYP_DataIn(*(uint32_t*)(inputaddr));
  534. inputaddr+=4;
  535. CRYP_DataIn(*(uint32_t*)(inputaddr));
  536. inputaddr+=4;
  537. CRYP_DataIn(*(uint32_t*)(inputaddr));
  538. inputaddr+=4;
  539. CRYP_DataIn(*(uint32_t*)(inputaddr));
  540. inputaddr+=4;
  541. /* Wait until the complete message has been processed */
  542. counter = 0;
  543. do
  544. {
  545. busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
  546. counter++;
  547. }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
  548. if (busystatus != RESET)
  549. {
  550. status = ERROR;
  551. }
  552. else
  553. {
  554. /* Read the Output block from the Output FIFO */
  555. *(uint32_t*)(outputaddr) = CRYP_DataOut();
  556. outputaddr+=4;
  557. *(uint32_t*)(outputaddr) = CRYP_DataOut();
  558. outputaddr+=4;
  559. *(uint32_t*)(outputaddr) = CRYP_DataOut();
  560. outputaddr+=4;
  561. *(uint32_t*)(outputaddr) = CRYP_DataOut();
  562. outputaddr+=4;
  563. }
  564. }
  565. /* Disable Crypto */
  566. CRYP_Cmd(DISABLE);
  567. return status;
  568. }
  569. /**
  570. * @brief Encrypt and decrypt using AES in GCM Mode. The GCM and CCM modes
  571. * are available only on STM32F437x Devices.
  572. * @param Mode: encryption or decryption Mode.
  573. * This parameter can be one of the following values:
  574. * @arg MODE_ENCRYPT: Encryption
  575. * @arg MODE_DECRYPT: Decryption
  576. * @param InitVectors: Initialisation Vectors used for AES algorithm.
  577. * @param Key: Key used for AES algorithm.
  578. * @param Keysize: length of the Key, must be a 128, 192 or 256.
  579. * @param Input: pointer to the Input buffer.
  580. * @param Ilength: length of the Input buffer in bytes, must be a multiple of 16.
  581. * @param Header: pointer to the header buffer.
  582. * @param Hlength: length of the header buffer in bytes, must be a multiple of 16.
  583. * @param Output: pointer to the returned buffer.
  584. * @param AuthTAG: pointer to the authentication TAG buffer.
  585. * @retval An ErrorStatus enumeration value:
  586. * - SUCCESS: Operation done
  587. * - ERROR: Operation failed
  588. */
  589. ErrorStatus CRYP_AES_GCM(uint8_t Mode, uint8_t InitVectors[16],
  590. uint8_t *Key, uint16_t Keysize,
  591. uint8_t *Input, uint32_t ILength,
  592. uint8_t *Header, uint32_t HLength,
  593. uint8_t *Output, uint8_t *AuthTAG)
  594. {
  595. CRYP_InitTypeDef AES_CRYP_InitStructure;
  596. CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure;
  597. CRYP_IVInitTypeDef AES_CRYP_IVInitStructure;
  598. __IO uint32_t counter = 0;
  599. uint32_t busystatus = 0;
  600. ErrorStatus status = SUCCESS;
  601. uint32_t keyaddr = (uint32_t)Key;
  602. uint32_t inputaddr = (uint32_t)Input;
  603. uint32_t outputaddr = (uint32_t)Output;
  604. uint32_t ivaddr = (uint32_t)InitVectors;
  605. uint32_t headeraddr = (uint32_t)Header;
  606. uint32_t tagaddr = (uint32_t)AuthTAG;
  607. uint64_t headerlength = HLength * 8;/* header length in bits */
  608. uint64_t inputlength = ILength * 8;/* input length in bits */
  609. uint32_t loopcounter = 0;
  610. /* Crypto structures initialisation*/
  611. CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure);
  612. switch(Keysize)
  613. {
  614. case 128:
  615. AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b;
  616. AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
  617. keyaddr+=4;
  618. AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
  619. keyaddr+=4;
  620. AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
  621. keyaddr+=4;
  622. AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
  623. break;
  624. case 192:
  625. AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b;
  626. AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
  627. keyaddr+=4;
  628. AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
  629. keyaddr+=4;
  630. AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
  631. keyaddr+=4;
  632. AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
  633. keyaddr+=4;
  634. AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
  635. keyaddr+=4;
  636. AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
  637. break;
  638. case 256:
  639. AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b;
  640. AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr));
  641. keyaddr+=4;
  642. AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr));
  643. keyaddr+=4;
  644. AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
  645. keyaddr+=4;
  646. AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
  647. keyaddr+=4;
  648. AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
  649. keyaddr+=4;
  650. AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
  651. keyaddr+=4;
  652. AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
  653. keyaddr+=4;
  654. AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
  655. break;
  656. default:
  657. break;
  658. }
  659. /* CRYP Initialization Vectors */
  660. AES_CRYP_IVInitStructure.CRYP_IV0Left = __REV(*(uint32_t*)(ivaddr));
  661. ivaddr+=4;
  662. AES_CRYP_IVInitStructure.CRYP_IV0Right= __REV(*(uint32_t*)(ivaddr));
  663. ivaddr+=4;
  664. AES_CRYP_IVInitStructure.CRYP_IV1Left = __REV(*(uint32_t*)(ivaddr));
  665. ivaddr+=4;
  666. AES_CRYP_IVInitStructure.CRYP_IV1Right= __REV(*(uint32_t*)(ivaddr));
  667. /*------------------ AES Encryption ------------------*/
  668. if(Mode == MODE_ENCRYPT) /* AES encryption */
  669. {
  670. /* Flush IN/OUT FIFOs */
  671. CRYP_FIFOFlush();
  672. /* Key Initialisation */
  673. CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
  674. /* CRYP Initialization Vectors */
  675. CRYP_IVInit(&AES_CRYP_IVInitStructure);
  676. /* Crypto Init for Key preparation for decryption process */
  677. AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
  678. AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_GCM;
  679. AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
  680. CRYP_Init(&AES_CRYP_InitStructure);
  681. /***************************** Init phase *********************************/
  682. /* Select init phase */
  683. CRYP_PhaseConfig(CRYP_Phase_Init);
  684. /* Enable Crypto processor */
  685. CRYP_Cmd(ENABLE);
  686. /* Wait for CRYPEN bit to be 0 */
  687. while(CRYP_GetCmdStatus() == ENABLE)
  688. {
  689. }
  690. /***************************** header phase *******************************/
  691. if(HLength != 0)
  692. {
  693. /* Select header phase */
  694. CRYP_PhaseConfig(CRYP_Phase_Header);
  695. /* Enable Crypto processor */
  696. CRYP_Cmd(ENABLE);
  697. if(CRYP_GetCmdStatus() == DISABLE)
  698. {
  699. /* The CRYP peripheral clock is not enabled or the device doesn't embed
  700. the CRYP peripheral (please check the device sales type. */
  701. return(ERROR);
  702. }
  703. for(loopcounter = 0; (loopcounter < HLength); loopcounter+=16)
  704. {
  705. /* Wait until the IFEM flag is reset */
  706. while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET)
  707. {
  708. }
  709. /* Write the Input block in the IN FIFO */
  710. CRYP_DataIn(*(uint32_t*)(headeraddr));
  711. headeraddr+=4;
  712. CRYP_DataIn(*(uint32_t*)(headeraddr));
  713. headeraddr+=4;
  714. CRYP_DataIn(*(uint32_t*)(headeraddr));
  715. headeraddr+=4;
  716. CRYP_DataIn(*(uint32_t*)(headeraddr));
  717. headeraddr+=4;
  718. }
  719. /* Wait until the complete message has been processed */
  720. counter = 0;
  721. do
  722. {
  723. busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
  724. counter++;
  725. }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
  726. if (busystatus != RESET)
  727. {
  728. status = ERROR;
  729. }
  730. }
  731. /**************************** payload phase *******************************/
  732. if(ILength != 0)
  733. {
  734. /* Select payload phase */
  735. CRYP_PhaseConfig(CRYP_Phase_Payload);
  736. /* Enable Crypto processor */
  737. CRYP_Cmd(ENABLE);
  738. if(CRYP_GetCmdStatus() == DISABLE)
  739. {
  740. /* The CRYP peripheral clock is not enabled or the device doesn't embed
  741. the CRYP peripheral (please check the device sales type. */
  742. return(ERROR);
  743. }
  744. for(loopcounter = 0; ((loopcounter < ILength) && (status != ERROR)); loopcounter+=16)
  745. {
  746. /* Wait until the IFEM flag is reset */
  747. while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET)
  748. {
  749. }
  750. /* Write the Input block in the IN FIFO */
  751. CRYP_DataIn(*(uint32_t*)(inputaddr));
  752. inputaddr+=4;
  753. CRYP_DataIn(*(uint32_t*)(inputaddr));
  754. inputaddr+=4;
  755. CRYP_DataIn(*(uint32_t*)(inputaddr));
  756. inputaddr+=4;
  757. CRYP_DataIn(*(uint32_t*)(inputaddr));
  758. inputaddr+=4;
  759. /* Wait until the complete message has been processed */
  760. counter = 0;
  761. do
  762. {
  763. busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
  764. counter++;
  765. }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
  766. if (busystatus != RESET)
  767. {
  768. status = ERROR;
  769. }
  770. else
  771. {
  772. /* Wait until the OFNE flag is reset */
  773. while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET)
  774. {
  775. }
  776. /* Read the Output block from the Output FIFO */
  777. *(uint32_t*)(outputaddr) = CRYP_DataOut();
  778. outputaddr+=4;
  779. *(uint32_t*)(outputaddr) = CRYP_DataOut();
  780. outputaddr+=4;
  781. *(uint32_t*)(outputaddr) = CRYP_DataOut();
  782. outputaddr+=4;
  783. *(uint32_t*)(outputaddr) = CRYP_DataOut();
  784. outputaddr+=4;
  785. }
  786. }
  787. }
  788. /***************************** final phase ********************************/
  789. /* Select final phase */
  790. CRYP_PhaseConfig(CRYP_Phase_Final);
  791. /* Enable Crypto processor */
  792. CRYP_Cmd(ENABLE);
  793. if(CRYP_GetCmdStatus() == DISABLE)
  794. {
  795. /* The CRYP peripheral clock is not enabled or the device doesn't embed
  796. the CRYP peripheral (please check the device sales type. */
  797. return(ERROR);
  798. }
  799. /* Write number of bits concatenated with header in the IN FIFO */
  800. CRYP_DataIn(__REV(headerlength>>32));
  801. CRYP_DataIn(__REV(headerlength));
  802. CRYP_DataIn(__REV(inputlength>>32));
  803. CRYP_DataIn(__REV(inputlength));
  804. /* Wait until the OFNE flag is reset */
  805. while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET)
  806. {
  807. }
  808. tagaddr = (uint32_t)AuthTAG;
  809. /* Read the Auth TAG in the IN FIFO */
  810. *(uint32_t*)(tagaddr) = CRYP_DataOut();
  811. tagaddr+=4;
  812. *(uint32_t*)(tagaddr) = CRYP_DataOut();
  813. tagaddr+=4;
  814. *(uint32_t*)(tagaddr) = CRYP_DataOut();
  815. tagaddr+=4;
  816. *(uint32_t*)(tagaddr) = CRYP_DataOut();
  817. tagaddr+=4;
  818. }
  819. /*------------------ AES Decryption ------------------*/
  820. else /* AES decryption */
  821. {
  822. /* Flush IN/OUT FIFOs */
  823. CRYP_FIFOFlush();
  824. /* Key Initialisation */
  825. CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
  826. /* CRYP Initialization Vectors */
  827. CRYP_IVInit(&AES_CRYP_IVInitStructure);
  828. /* Crypto Init for Key preparation for decryption process */
  829. AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
  830. AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_GCM;
  831. AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
  832. CRYP_Init(&AES_CRYP_InitStructure);
  833. /***************************** Init phase *********************************/
  834. /* Select init phase */
  835. CRYP_PhaseConfig(CRYP_Phase_Init);
  836. /* Enable Crypto processor */
  837. CRYP_Cmd(ENABLE);
  838. /* Wait for CRYPEN bit to be 0 */
  839. while(CRYP_GetCmdStatus() == ENABLE)
  840. {
  841. }
  842. /***************************** header phase *******************************/
  843. if(HLength != 0)
  844. {
  845. /* Select header phase */
  846. CRYP_PhaseConfig(CRYP_Phase_Header);
  847. /* Enable Crypto processor */
  848. CRYP_Cmd(ENABLE);
  849. if(CRYP_GetCmdStatus() == DISABLE)
  850. {
  851. /* The CRYP peripheral clock is not enabled or the device doesn't embed
  852. the CRYP peripheral (please check the device sales type. */
  853. return(ERROR);
  854. }
  855. for(loopcounter = 0; (loopcounter < HLength); loopcounter+=16)
  856. {
  857. /* Wait until the IFEM flag is reset */
  858. while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET)
  859. {
  860. }
  861. /* Write the Input block in the IN FIFO */
  862. CRYP_DataIn(*(uint32_t*)(headeraddr));
  863. headeraddr+=4;
  864. CRYP_DataIn(*(uint32_t*)(headeraddr));
  865. headeraddr+=4;
  866. CRYP_DataIn(*(uint32_t*)(headeraddr));
  867. headeraddr+=4;
  868. CRYP_DataIn(*(uint32_t*)(headeraddr));
  869. headeraddr+=4;
  870. }
  871. /* Wait until the complete message has been processed */
  872. counter = 0;
  873. do
  874. {
  875. busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
  876. counter++;
  877. }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
  878. if (busystatus != RESET)
  879. {
  880. status = ERROR;
  881. }
  882. }
  883. /**************************** payload phase *******************************/
  884. if(ILength != 0)
  885. {
  886. /* Select payload phase */
  887. CRYP_PhaseConfig(CRYP_Phase_Payload);
  888. /* Enable Crypto processor */
  889. CRYP_Cmd(ENABLE);
  890. if(CRYP_GetCmdStatus() == DISABLE)
  891. {
  892. /* The CRYP peripheral clock is not enabled or the device doesn't embed
  893. the CRYP peripheral (please check the device sales type. */
  894. return(ERROR);
  895. }
  896. for(loopcounter = 0; ((loopcounter < ILength) && (status != ERROR)); loopcounter+=16)
  897. {
  898. /* Wait until the IFEM flag is reset */
  899. while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET)
  900. {
  901. }
  902. /* Write the Input block in the IN FIFO */
  903. CRYP_DataIn(*(uint32_t*)(inputaddr));
  904. inputaddr+=4;
  905. CRYP_DataIn(*(uint32_t*)(inputaddr));
  906. inputaddr+=4;
  907. CRYP_DataIn(*(uint32_t*)(inputaddr));
  908. inputaddr+=4;
  909. CRYP_DataIn(*(uint32_t*)(inputaddr));
  910. inputaddr+=4;
  911. /* Wait until the complete message has been processed */
  912. counter = 0;
  913. do
  914. {
  915. busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
  916. counter++;
  917. }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
  918. if (busystatus != RESET)
  919. {
  920. status = ERROR;
  921. }
  922. else
  923. {
  924. /* Wait until the OFNE flag is reset */
  925. while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET)
  926. {
  927. }
  928. /* Read the Output block from the Output FIFO */
  929. *(uint32_t*)(outputaddr) = CRYP_DataOut();
  930. outputaddr+=4;
  931. *(uint32_t*)(outputaddr) = CRYP_DataOut();
  932. outputaddr+=4;
  933. *(uint32_t*)(outputaddr) = CRYP_DataOut();
  934. outputaddr+=4;
  935. *(uint32_t*)(outputaddr) = CRYP_DataOut();
  936. outputaddr+=4;
  937. }
  938. }
  939. }
  940. /***************************** final phase ********************************/
  941. /* Select final phase */
  942. CRYP_PhaseConfig(CRYP_Phase_Final);
  943. /* Enable Crypto processor */
  944. CRYP_Cmd(ENABLE);
  945. if(CRYP_GetCmdStatus() == DISABLE)
  946. {
  947. /* The CRYP peripheral clock is not enabled or the device doesn't embed
  948. the CRYP peripheral (please check the device sales type. */
  949. return(ERROR);
  950. }
  951. /* Write number of bits concatenated with header in the IN FIFO */
  952. CRYP_DataIn(__REV(headerlength>>32));
  953. CRYP_DataIn(__REV(headerlength));
  954. CRYP_DataIn(__REV(inputlength>>32));
  955. CRYP_DataIn(__REV(inputlength));
  956. /* Wait until the OFNE flag is reset */
  957. while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET)
  958. {
  959. }
  960. tagaddr = (uint32_t)AuthTAG;
  961. /* Read the Auth TAG in the IN FIFO */
  962. *(uint32_t*)(tagaddr) = CRYP_DataOut();
  963. tagaddr+=4;
  964. *(uint32_t*)(tagaddr) = CRYP_DataOut();
  965. tagaddr+=4;
  966. *(uint32_t*)(tagaddr) = CRYP_DataOut();
  967. tagaddr+=4;
  968. *(uint32_t*)(tagaddr) = CRYP_DataOut();
  969. tagaddr+=4;
  970. }
  971. /* Disable Crypto */
  972. CRYP_Cmd(DISABLE);
  973. return status;
  974. }
  975. /**
  976. * @brief Encrypt and decrypt using AES in CCM Mode. The GCM and CCM modes
  977. * are available only on STM32F437x Devices.
  978. * @param Mode: encryption or decryption Mode.
  979. * This parameter can be one of the following values:
  980. * @arg MODE_ENCRYPT: Encryption
  981. * @arg MODE_DECRYPT: Decryption
  982. * @param Nonce: the nonce used for AES algorithm. It shall be unique for each processing.
  983. * @param Key: Key used for AES algorithm.
  984. * @param Keysize: length of the Key, must be a 128, 192 or 256.
  985. * @param Input: pointer to the Input buffer.
  986. * @param Ilength: length of the Input buffer in bytes, must be a multiple of 16.
  987. * @param Header: pointer to the header buffer.
  988. * @param Hlength: length of the header buffer in bytes.
  989. * @param HBuffer: pointer to temporary buffer used to append the header
  990. * HBuffer size must be equal to Hlength + 21
  991. * @param Output: pointer to the returned buffer.
  992. * @param AuthTAG: pointer to the authentication TAG buffer.
  993. * @param TAGSize: the size of the TAG (called also MAC).
  994. * @retval An ErrorStatus enumeration value:
  995. * - SUCCESS: Operation done
  996. * - ERROR: Operation failed
  997. */
  998. ErrorStatus CRYP_AES_CCM(uint8_t Mode,
  999. uint8_t* Nonce, uint32_t NonceSize,
  1000. uint8_t *Key, uint16_t Keysize,
  1001. uint8_t *Input, uint32_t ILength,
  1002. uint8_t *Header, uint32_t HLength, uint8_t *HBuffer,
  1003. uint8_t *Output,
  1004. uint8_t *AuthTAG, uint32_t TAGSize)
  1005. {
  1006. CRYP_InitTypeDef AES_CRYP_InitStructure;
  1007. CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure;
  1008. CRYP_IVInitTypeDef AES_CRYP_IVInitStructure;
  1009. __IO uint32_t counter = 0;
  1010. uint32_t busystatus = 0;
  1011. ErrorStatus status = SUCCESS;
  1012. uint32_t keyaddr = (uint32_t)Key;
  1013. uint32_t inputaddr = (uint32_t)Input;
  1014. uint32_t outputaddr = (uint32_t)Output;
  1015. uint32_t headeraddr = (uint32_t)Header;
  1016. uint32_t tagaddr = (uint32_t)AuthTAG;
  1017. uint32_t headersize = HLength;
  1018. uint32_t loopcounter = 0;
  1019. uint32_t bufferidx = 0;
  1020. uint8_t blockb0[16] = {0};/* Block B0 */
  1021. uint8_t ctr[16] = {0}; /* Counter */
  1022. uint32_t temptag[4] = {0}; /* temporary TAG (MAC) */
  1023. uint32_t ctraddr = (uint32_t)ctr;
  1024. uint32_t b0addr = (uint32_t)blockb0;
  1025. /************************ Formatting the header block ***********************/
  1026. if(headersize != 0)
  1027. {
  1028. /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
  1029. if(headersize < 65280)
  1030. {
  1031. HBuffer[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
  1032. HBuffer[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
  1033. headersize += 2;
  1034. }
  1035. else
  1036. {
  1037. /* header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
  1038. HBuffer[bufferidx++] = 0xFF;
  1039. HBuffer[bufferidx++] = 0xFE;
  1040. HBuffer[bufferidx++] = headersize & 0xff000000;
  1041. HBuffer[bufferidx++] = headersize & 0x00ff0000;
  1042. HBuffer[bufferidx++] = headersize & 0x0000ff00;
  1043. HBuffer[bufferidx++] = headersize & 0x000000ff;
  1044. headersize += 6;
  1045. }
  1046. /* Copy the header buffer in internal buffer "HBuffer" */
  1047. for(loopcounter = 0; loopcounter < headersize; loopcounter++)
  1048. {
  1049. HBuffer[bufferidx++] = Header[loopcounter];
  1050. }
  1051. /* Check if the header size is modulo 16 */
  1052. if ((headersize % 16) != 0)
  1053. {
  1054. /* Padd the header buffer with 0s till the HBuffer length is modulo 16 */
  1055. for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
  1056. {
  1057. HBuffer[loopcounter] = 0;
  1058. }
  1059. /* Set the header size to modulo 16 */
  1060. headersize = ((headersize/16) + 1) * 16;
  1061. }
  1062. /* set the pointer headeraddr to HBuffer */
  1063. headeraddr = (uint32_t)HBuffer;
  1064. }
  1065. /************************* Formatting the block B0 **************************/
  1066. if(headersize != 0)
  1067. {
  1068. blockb0[0] = 0x40;
  1069. }
  1070. /* Flags byte */
  1071. blockb0[0] |= 0u | (((( (uint8_t) TAGSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - NonceSize) - 1) & 0x07);
  1072. for (loopcounter = 0; loopcounter < NonceSize; loopcounter++)
  1073. {
  1074. blockb0[loopcounter+1] = Nonce[loopcounter];
  1075. }
  1076. for ( ; loopcounter < 13; loopcounter++)
  1077. {
  1078. blockb0[loopcounter+1] = 0;
  1079. }
  1080. blockb0[14] = ((ILength >> 8) & 0xFF);
  1081. blockb0[15] = (ILength & 0xFF);
  1082. /************************* Formatting the initial counter *******************/
  1083. /* Byte 0:
  1084. Bits 7 and 6 are reserved and shall be set to 0
  1085. Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter blocks
  1086. are distinct from B0
  1087. Bits 0, 1, and 2 contain the same encoding of q as in B0
  1088. */
  1089. ctr[0] = blockb0[0] & 0x07;
  1090. /* byte 1 to NonceSize is the IV (Nonce) */
  1091. for(loopcounter = 1; loopcounter < NonceSize + 1; loopcounter++)
  1092. {
  1093. ctr[loopcounter] = blockb0[loopcounter];
  1094. }
  1095. /* Set the LSB to 1 */
  1096. ctr[15] |= 0x01;
  1097. /* Crypto structures initialisation*/
  1098. CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure);
  1099. switch(Keysize)
  1100. {
  1101. case 128:
  1102. AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b;
  1103. AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
  1104. keyaddr+=4;
  1105. AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
  1106. keyaddr+=4;
  1107. AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
  1108. keyaddr+=4;
  1109. AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
  1110. break;
  1111. case 192:
  1112. AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b;
  1113. AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
  1114. keyaddr+=4;
  1115. AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
  1116. keyaddr+=4;
  1117. AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
  1118. keyaddr+=4;
  1119. AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
  1120. keyaddr+=4;
  1121. AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
  1122. keyaddr+=4;
  1123. AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
  1124. break;
  1125. case 256:
  1126. AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b;
  1127. AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr));
  1128. keyaddr+=4;
  1129. AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr));
  1130. keyaddr+=4;
  1131. AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
  1132. keyaddr+=4;
  1133. AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
  1134. keyaddr+=4;
  1135. AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
  1136. keyaddr+=4;
  1137. AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
  1138. keyaddr+=4;
  1139. AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
  1140. keyaddr+=4;
  1141. AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
  1142. break;
  1143. default:
  1144. break;
  1145. }
  1146. /* CRYP Initialization Vectors */
  1147. AES_CRYP_IVInitStructure.CRYP_IV0Left = (__REV(*(uint32_t*)(ctraddr)));
  1148. ctraddr+=4;
  1149. AES_CRYP_IVInitStructure.CRYP_IV0Right= (__REV(*(uint32_t*)(ctraddr)));
  1150. ctraddr+=4;
  1151. AES_CRYP_IVInitStructure.CRYP_IV1Left = (__REV(*(uint32_t*)(ctraddr)));
  1152. ctraddr+=4;
  1153. AES_CRYP_IVInitStructure.CRYP_IV1Right= (__REV(*(uint32_t*)(ctraddr)));
  1154. /*------------------ AES Encryption ------------------*/
  1155. if(Mode == MODE_ENCRYPT) /* AES encryption */
  1156. {
  1157. /* Flush IN/OUT FIFOs */
  1158. CRYP_FIFOFlush();
  1159. /* Key Initialisation */
  1160. CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
  1161. /* CRYP Initialization Vectors */
  1162. CRYP_IVInit(&AES_CRYP_IVInitStructure);
  1163. /* Crypto Init for Key preparation for decryption process */
  1164. AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
  1165. AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_CCM;
  1166. AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
  1167. CRYP_Init(&AES_CRYP_InitStructure);
  1168. /***************************** Init phase *********************************/
  1169. /* Select init phase */
  1170. CRYP_PhaseConfig(CRYP_Phase_Init);
  1171. b0addr = (uint32_t)blockb0;
  1172. /* Write the blockb0 block in the IN FIFO */
  1173. CRYP_DataIn((*(uint32_t*)(b0addr)));
  1174. b0addr+=4;
  1175. CRYP_DataIn((*(uint32_t*)(b0addr)));
  1176. b0addr+=4;
  1177. CRYP_DataIn((*(uint32_t*)(b0addr)));
  1178. b0addr+=4;
  1179. CRYP_DataIn((*(uint32_t*)(b0addr)));
  1180. /* Enable Crypto processor */
  1181. CRYP_Cmd(ENABLE);
  1182. /* Wait for CRYPEN bit to be 0 */
  1183. while(CRYP_GetCmdStatus() == ENABLE)
  1184. {
  1185. }
  1186. /***************************** header phase *******************************/
  1187. if(headersize != 0)
  1188. {
  1189. /* Select header phase */
  1190. CRYP_PhaseConfig(CRYP_Phase_Header);
  1191. /* Enable Crypto processor */
  1192. CRYP_Cmd(ENABLE);
  1193. if(CRYP_GetCmdStatus() == DISABLE)
  1194. {
  1195. /* The CRYP peripheral clock is not enabled or the device doesn't embed
  1196. the CRYP peripheral (please check the device sales type. */
  1197. return(ERROR);
  1198. }
  1199. for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
  1200. {
  1201. /* Wait until the IFEM flag is reset */
  1202. while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET)
  1203. {
  1204. }
  1205. /* Write the Input block in the IN FIFO */
  1206. CRYP_DataIn(*(uint32_t*)(headeraddr));
  1207. headeraddr+=4;
  1208. CRYP_DataIn(*(uint32_t*)(headeraddr));
  1209. headeraddr+=4;
  1210. CRYP_DataIn(*(uint32_t*)(headeraddr));
  1211. headeraddr+=4;
  1212. CRYP_DataIn(*(uint32_t*)(headeraddr));
  1213. headeraddr+=4;
  1214. }
  1215. /* Wait until the complete message has been processed */
  1216. counter = 0;
  1217. do
  1218. {
  1219. busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
  1220. counter++;
  1221. }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
  1222. if (busystatus != RESET)
  1223. {
  1224. status = ERROR;
  1225. }
  1226. }
  1227. /**************************** payload phase *******************************/
  1228. if(ILength != 0)
  1229. {
  1230. /* Select payload phase */
  1231. CRYP_PhaseConfig(CRYP_Phase_Payload);
  1232. /* Enable Crypto processor */
  1233. CRYP_Cmd(ENABLE);
  1234. if(CRYP_GetCmdStatus() == DISABLE)
  1235. {
  1236. /* The CRYP peripheral clock is not enabled or the device doesn't embed
  1237. the CRYP peripheral (please check the device sales type. */
  1238. return(ERROR);
  1239. }
  1240. for(loopcounter = 0; ((loopcounter < ILength) && (status != ERROR)); loopcounter+=16)
  1241. {
  1242. /* Wait until the IFEM flag is reset */
  1243. while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET)
  1244. {
  1245. }
  1246. /* Write the Input block in the IN FIFO */
  1247. CRYP_DataIn(*(uint32_t*)(inputaddr));
  1248. inputaddr+=4;
  1249. CRYP_DataIn(*(uint32_t*)(inputaddr));
  1250. inputaddr+=4;
  1251. CRYP_DataIn(*(uint32_t*)(inputaddr));
  1252. inputaddr+=4;
  1253. CRYP_DataIn(*(uint32_t*)(inputaddr));
  1254. inputaddr+=4;
  1255. /* Wait until the complete message has been processed */
  1256. counter = 0;
  1257. do
  1258. {
  1259. busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
  1260. counter++;
  1261. }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
  1262. if (busystatus != RESET)
  1263. {
  1264. status = ERROR;
  1265. }
  1266. else
  1267. {
  1268. /* Wait until the OFNE flag is reset */
  1269. while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET)
  1270. {
  1271. }
  1272. /* Read the Output block from the Output FIFO */
  1273. *(uint32_t*)(outputaddr) = CRYP_DataOut();
  1274. outputaddr+=4;
  1275. *(uint32_t*)(outputaddr) = CRYP_DataOut();
  1276. outputaddr+=4;
  1277. *(uint32_t*)(outputaddr) = CRYP_DataOut();
  1278. outputaddr+=4;
  1279. *(uint32_t*)(outputaddr) = CRYP_DataOut();
  1280. outputaddr+=4;
  1281. }
  1282. }
  1283. }
  1284. /***************************** final phase ********************************/
  1285. /* Select final phase */
  1286. CRYP_PhaseConfig(CRYP_Phase_Final);
  1287. /* Enable Crypto processor */
  1288. CRYP_Cmd(ENABLE);
  1289. if(CRYP_GetCmdStatus() == DISABLE)
  1290. {
  1291. /* The CRYP peripheral clock is not enabled or the device doesn't embed
  1292. the CRYP peripheral (please check the device sales type. */
  1293. return(ERROR);
  1294. }
  1295. ctraddr = (uint32_t)ctr;
  1296. /* Write the counter block in the IN FIFO */
  1297. CRYP_DataIn(*(uint32_t*)(ctraddr));
  1298. ctraddr+=4;
  1299. CRYP_DataIn(*(uint32_t*)(ctraddr));
  1300. ctraddr+=4;
  1301. CRYP_DataIn(*(uint32_t*)(ctraddr));
  1302. ctraddr+=4;
  1303. /* Reset bit 0 (after 8-bit swap) is equivalent to reset bit 24 (before 8-bit swap) */
  1304. CRYP_DataIn(*(uint32_t*)(ctraddr) & 0xfeffffff);
  1305. /* Wait until the OFNE flag is reset */
  1306. while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET)
  1307. {
  1308. }
  1309. /* Read the Auth TAG in the IN FIFO */
  1310. temptag[0] = CRYP_DataOut();
  1311. temptag[1] = CRYP_DataOut();
  1312. temptag[2] = CRYP_DataOut();
  1313. temptag[3] = CRYP_DataOut();
  1314. }
  1315. /*------------------ AES Decryption ------------------*/
  1316. else /* AES decryption */
  1317. {
  1318. /* Flush IN/OUT FIFOs */
  1319. CRYP_FIFOFlush();
  1320. /* Key Initialisation */
  1321. CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
  1322. /* CRYP Initialization Vectors */
  1323. CRYP_IVInit(&AES_CRYP_IVInitStructure);
  1324. /* Crypto Init for Key preparation for decryption process */
  1325. AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
  1326. AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_CCM;
  1327. AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
  1328. CRYP_Init(&AES_CRYP_InitStructure);
  1329. /***************************** Init phase *********************************/
  1330. /* Select init phase */
  1331. CRYP_PhaseConfig(CRYP_Phase_Init);
  1332. b0addr = (uint32_t)blockb0;
  1333. /* Write the blockb0 block in the IN FIFO */
  1334. CRYP_DataIn((*(uint32_t*)(b0addr)));
  1335. b0addr+=4;
  1336. CRYP_DataIn((*(uint32_t*)(b0addr)));
  1337. b0addr+=4;
  1338. CRYP_DataIn((*(uint32_t*)(b0addr)));
  1339. b0addr+=4;
  1340. CRYP_DataIn((*(uint32_t*)(b0addr)));
  1341. /* Enable Crypto processor */
  1342. CRYP_Cmd(ENABLE);
  1343. /* Wait for CRYPEN bit to be 0 */
  1344. while(CRYP_GetCmdStatus() == ENABLE)
  1345. {
  1346. }
  1347. /***************************** header phase *******************************/
  1348. if(headersize != 0)
  1349. {
  1350. /* Select header phase */
  1351. CRYP_PhaseConfig(CRYP_Phase_Header);
  1352. /* Enable Crypto processor */
  1353. CRYP_Cmd(ENABLE);
  1354. if(CRYP_GetCmdStatus() == DISABLE)
  1355. {
  1356. /* The CRYP peripheral clock is not enabled or the device doesn't embed
  1357. the CRYP peripheral (please check the device sales type. */
  1358. return(ERROR);
  1359. }
  1360. for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
  1361. {
  1362. /* Wait until the IFEM flag is reset */
  1363. while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET)
  1364. {
  1365. }
  1366. /* Write the Input block in the IN FIFO */
  1367. CRYP_DataIn(*(uint32_t*)(headeraddr));
  1368. headeraddr+=4;
  1369. CRYP_DataIn(*(uint32_t*)(headeraddr));
  1370. headeraddr+=4;
  1371. CRYP_DataIn(*(uint32_t*)(headeraddr));
  1372. headeraddr+=4;
  1373. CRYP_DataIn(*(uint32_t*)(headeraddr));
  1374. headeraddr+=4;
  1375. }
  1376. /* Wait until the complete message has been processed */
  1377. counter = 0;
  1378. do
  1379. {
  1380. busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
  1381. counter++;
  1382. }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
  1383. if (busystatus != RESET)
  1384. {
  1385. status = ERROR;
  1386. }
  1387. }
  1388. /**************************** payload phase *******************************/
  1389. if(ILength != 0)
  1390. {
  1391. /* Select payload phase */
  1392. CRYP_PhaseConfig(CRYP_Phase_Payload);
  1393. /* Enable Crypto processor */
  1394. CRYP_Cmd(ENABLE);
  1395. if(CRYP_GetCmdStatus() == DISABLE)
  1396. {
  1397. /* The CRYP peripheral clock is not enabled or the device doesn't embed
  1398. the CRYP peripheral (please check the device sales type. */
  1399. return(ERROR);
  1400. }
  1401. for(loopcounter = 0; ((loopcounter < ILength) && (status != ERROR)); loopcounter+=16)
  1402. {
  1403. /* Wait until the IFEM flag is reset */
  1404. while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET)
  1405. {
  1406. }
  1407. /* Write the Input block in the IN FIFO */
  1408. CRYP_DataIn(*(uint32_t*)(inputaddr));
  1409. inputaddr+=4;
  1410. CRYP_DataIn(*(uint32_t*)(inputaddr));
  1411. inputaddr+=4;
  1412. CRYP_DataIn(*(uint32_t*)(inputaddr));
  1413. inputaddr+=4;
  1414. CRYP_DataIn(*(uint32_t*)(inputaddr));
  1415. inputaddr+=4;
  1416. /* Wait until the complete message has been processed */
  1417. counter = 0;
  1418. do
  1419. {
  1420. busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
  1421. counter++;
  1422. }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
  1423. if (busystatus != RESET)
  1424. {
  1425. status = ERROR;
  1426. }
  1427. else
  1428. {
  1429. /* Wait until the OFNE flag is reset */
  1430. while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET)
  1431. {
  1432. }
  1433. /* Read the Output block from the Output FIFO */
  1434. *(uint32_t*)(outputaddr) = CRYP_DataOut();
  1435. outputaddr+=4;
  1436. *(uint32_t*)(outputaddr) = CRYP_DataOut();
  1437. outputaddr+=4;
  1438. *(uint32_t*)(outputaddr) = CRYP_DataOut();
  1439. outputaddr+=4;
  1440. *(uint32_t*)(outputaddr) = CRYP_DataOut();
  1441. outputaddr+=4;
  1442. }
  1443. }
  1444. }
  1445. /***************************** final phase ********************************/
  1446. /* Select final phase */
  1447. CRYP_PhaseConfig(CRYP_Phase_Final);
  1448. /* Enable Crypto processor */
  1449. CRYP_Cmd(ENABLE);
  1450. if(CRYP_GetCmdStatus() == DISABLE)
  1451. {
  1452. /* The CRYP peripheral clock is not enabled or the device doesn't embed
  1453. the CRYP peripheral (please check the device sales type. */
  1454. return(ERROR);
  1455. }
  1456. ctraddr = (uint32_t)ctr;
  1457. /* Write the counter block in the IN FIFO */
  1458. CRYP_DataIn(*(uint32_t*)(ctraddr));
  1459. ctraddr+=4;
  1460. CRYP_DataIn(*(uint32_t*)(ctraddr));
  1461. ctraddr+=4;
  1462. CRYP_DataIn(*(uint32_t*)(ctraddr));
  1463. ctraddr+=4;
  1464. /* Reset bit 0 (after 8-bit swap) is equivalent to reset bit 24 (before 8-bit swap) */
  1465. CRYP_DataIn(*(uint32_t*)(ctraddr) & 0xfeffffff);
  1466. /* Wait until the OFNE flag is reset */
  1467. while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET)
  1468. {
  1469. }
  1470. /* Read the Authentification TAG (MAC) in the IN FIFO */
  1471. temptag[0] = CRYP_DataOut();
  1472. temptag[1] = CRYP_DataOut();
  1473. temptag[2] = CRYP_DataOut();
  1474. temptag[3] = CRYP_DataOut();
  1475. }
  1476. /* Copy temporary authentication TAG in user TAG buffer */
  1477. for(loopcounter = 0; (loopcounter < TAGSize); loopcounter++)
  1478. {
  1479. /* Set the authentication TAG buffer */
  1480. *((uint8_t*)tagaddr+loopcounter) = *((uint8_t*)temptag+loopcounter);
  1481. }
  1482. /* Disable Crypto */
  1483. CRYP_Cmd(DISABLE);
  1484. return status;
  1485. }
  1486. /**
  1487. * @}
  1488. */
  1489. /**
  1490. * @}
  1491. */
  1492. /**
  1493. * @}
  1494. */
  1495. /**
  1496. * @}
  1497. */