stm32f4xx_wwdg.c 9.5 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f4xx_wwdg.c
  4. * @author MCD Application Team
  5. * @version V1.8.1
  6. * @date 27-January-2022
  7. * @brief This file provides firmware functions to manage the following
  8. * functionalities of the Window watchdog (WWDG) peripheral:
  9. * + Prescaler, Refresh window and Counter configuration
  10. * + WWDG activation
  11. * + Interrupts and flags management
  12. *
  13. @verbatim
  14. ===============================================================================
  15. ##### WWDG features #####
  16. ===============================================================================
  17. [..]
  18. Once enabled the WWDG generates a system reset on expiry of a programmed
  19. time period, unless the program refreshes the counter (downcounter)
  20. before to reach 0x3F value (i.e. a reset is generated when the counter
  21. value rolls over from 0x40 to 0x3F).
  22. An MCU reset is also generated if the counter value is refreshed
  23. before the counter has reached the refresh window value. This
  24. implies that the counter must be refreshed in a limited window.
  25. Once enabled the WWDG cannot be disabled except by a system reset.
  26. WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
  27. reset occurs.
  28. The WWDG counter input clock is derived from the APB clock divided
  29. by a programmable prescaler.
  30. WWDG counter clock = PCLK1 / Prescaler
  31. WWDG timeout = (WWDG counter clock) * (counter value)
  32. Min-max timeout value @42 MHz(PCLK1): ~97.5 us / ~49.9 ms
  33. ##### How to use this driver #####
  34. ===============================================================================
  35. [..]
  36. (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) function
  37. (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function
  38. (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function
  39. (#) Set the WWDG counter value and start it using WWDG_Enable() function.
  40. When the WWDG is enabled the counter value should be configured to
  41. a value greater than 0x40 to prevent generating an immediate reset.
  42. (#) Optionally you can enable the Early wakeup interrupt which is
  43. generated when the counter reach 0x40.
  44. Once enabled this interrupt cannot be disabled except by a system reset.
  45. (#) Then the application program must refresh the WWDG counter at regular
  46. intervals during normal operation to prevent an MCU reset, using
  47. WWDG_SetCounter() function. This operation must occur only when
  48. the counter value is lower than the refresh window value,
  49. programmed using WWDG_SetWindowValue().
  50. @endverbatim
  51. ******************************************************************************
  52. * @attention
  53. *
  54. * Copyright (c) 2016 STMicroelectronics.
  55. * All rights reserved.
  56. *
  57. * This software is licensed under terms that can be found in the LICENSE file
  58. * in the root directory of this software component.
  59. * If no LICENSE file comes with this software, it is provided AS-IS.
  60. *
  61. ******************************************************************************
  62. */
  63. /* Includes ------------------------------------------------------------------*/
  64. #include "stm32f4xx_wwdg.h"
  65. #include "stm32f4xx_rcc.h"
  66. /** @addtogroup STM32F4xx_StdPeriph_Driver
  67. * @{
  68. */
  69. /** @defgroup WWDG
  70. * @brief WWDG driver modules
  71. * @{
  72. */
  73. /* Private typedef -----------------------------------------------------------*/
  74. /* Private define ------------------------------------------------------------*/
  75. /* ----------- WWDG registers bit address in the alias region ----------- */
  76. #define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)
  77. /* Alias word address of EWI bit */
  78. #define CFR_OFFSET (WWDG_OFFSET + 0x04)
  79. #define EWI_BitNumber 0x09
  80. #define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
  81. /* --------------------- WWDG registers bit mask ------------------------ */
  82. /* CFR register bit mask */
  83. #define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F)
  84. #define CFR_W_MASK ((uint32_t)0xFFFFFF80)
  85. #define BIT_MASK ((uint8_t)0x7F)
  86. /* Private macro -------------------------------------------------------------*/
  87. /* Private variables ---------------------------------------------------------*/
  88. /* Private function prototypes -----------------------------------------------*/
  89. /* Private functions ---------------------------------------------------------*/
  90. /** @defgroup WWDG_Private_Functions
  91. * @{
  92. */
  93. /** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions
  94. * @brief Prescaler, Refresh window and Counter configuration functions
  95. *
  96. @verbatim
  97. ===============================================================================
  98. ##### Prescaler, Refresh window and Counter configuration functions #####
  99. ===============================================================================
  100. @endverbatim
  101. * @{
  102. */
  103. /**
  104. * @brief Deinitializes the WWDG peripheral registers to their default reset values.
  105. * @param None
  106. * @retval None
  107. */
  108. void WWDG_DeInit(void)
  109. {
  110. RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
  111. RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
  112. }
  113. /**
  114. * @brief Sets the WWDG Prescaler.
  115. * @param WWDG_Prescaler: specifies the WWDG Prescaler.
  116. * This parameter can be one of the following values:
  117. * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
  118. * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
  119. * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
  120. * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
  121. * @retval None
  122. */
  123. void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
  124. {
  125. uint32_t tmpreg = 0;
  126. /* Check the parameters */
  127. assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
  128. /* Clear WDGTB[1:0] bits */
  129. tmpreg = WWDG->CFR & CFR_WDGTB_MASK;
  130. /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
  131. tmpreg |= WWDG_Prescaler;
  132. /* Store the new value */
  133. WWDG->CFR = tmpreg;
  134. }
  135. /**
  136. * @brief Sets the WWDG window value.
  137. * @param WindowValue: specifies the window value to be compared to the downcounter.
  138. * This parameter value must be lower than 0x80.
  139. * @retval None
  140. */
  141. void WWDG_SetWindowValue(uint8_t WindowValue)
  142. {
  143. __IO uint32_t tmpreg = 0;
  144. /* Check the parameters */
  145. assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
  146. /* Clear W[6:0] bits */
  147. tmpreg = WWDG->CFR & CFR_W_MASK;
  148. /* Set W[6:0] bits according to WindowValue value */
  149. tmpreg |= WindowValue & (uint32_t) BIT_MASK;
  150. /* Store the new value */
  151. WWDG->CFR = tmpreg;
  152. }
  153. /**
  154. * @brief Enables the WWDG Early Wakeup interrupt(EWI).
  155. * @note Once enabled this interrupt cannot be disabled except by a system reset.
  156. * @param None
  157. * @retval None
  158. */
  159. void WWDG_EnableIT(void)
  160. {
  161. *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
  162. }
  163. /**
  164. * @brief Sets the WWDG counter value.
  165. * @param Counter: specifies the watchdog counter value.
  166. * This parameter must be a number between 0x40 and 0x7F (to prevent generating
  167. * an immediate reset)
  168. * @retval None
  169. */
  170. void WWDG_SetCounter(uint8_t Counter)
  171. {
  172. /* Check the parameters */
  173. assert_param(IS_WWDG_COUNTER(Counter));
  174. /* Write to T[6:0] bits to configure the counter value, no need to do
  175. a read-modify-write; writing a 0 to WDGA bit does nothing */
  176. WWDG->CR = Counter & BIT_MASK;
  177. }
  178. /**
  179. * @}
  180. */
  181. /** @defgroup WWDG_Group2 WWDG activation functions
  182. * @brief WWDG activation functions
  183. *
  184. @verbatim
  185. ===============================================================================
  186. ##### WWDG activation function #####
  187. ===============================================================================
  188. @endverbatim
  189. * @{
  190. */
  191. /**
  192. * @brief Enables WWDG and load the counter value.
  193. * @param Counter: specifies the watchdog counter value.
  194. * This parameter must be a number between 0x40 and 0x7F (to prevent generating
  195. * an immediate reset)
  196. * @retval None
  197. */
  198. void WWDG_Enable(uint8_t Counter)
  199. {
  200. /* Check the parameters */
  201. assert_param(IS_WWDG_COUNTER(Counter));
  202. WWDG->CR = WWDG_CR_WDGA | Counter;
  203. }
  204. /**
  205. * @}
  206. */
  207. /** @defgroup WWDG_Group3 Interrupts and flags management functions
  208. * @brief Interrupts and flags management functions
  209. *
  210. @verbatim
  211. ===============================================================================
  212. ##### Interrupts and flags management functions #####
  213. ===============================================================================
  214. @endverbatim
  215. * @{
  216. */
  217. /**
  218. * @brief Checks whether the Early Wakeup interrupt flag is set or not.
  219. * @param None
  220. * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)
  221. */
  222. FlagStatus WWDG_GetFlagStatus(void)
  223. {
  224. FlagStatus bitstatus = RESET;
  225. if ((WWDG->SR) != (uint32_t)RESET)
  226. {
  227. bitstatus = SET;
  228. }
  229. else
  230. {
  231. bitstatus = RESET;
  232. }
  233. return bitstatus;
  234. }
  235. /**
  236. * @brief Clears Early Wakeup interrupt flag.
  237. * @param None
  238. * @retval None
  239. */
  240. void WWDG_ClearFlag(void)
  241. {
  242. WWDG->SR = (uint32_t)RESET;
  243. }
  244. /**
  245. * @}
  246. */
  247. /**
  248. * @}
  249. */
  250. /**
  251. * @}
  252. */
  253. /**
  254. * @}
  255. */