cpld/CPLD_Transmitter_tbb.vt

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/08/03 06:53:02
// Design Name: 
// Module Name: SimSortTest
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module CPLD_Transmitter_tbb(

    );
    reg SysClk=0;
	 reg BckIn = 0;   
	 reg LrckIn = 0;
    reg RstN = 1;
	 reg [16:0] DataIn = 1;
	 
	 integer counterIn;
    
    CPLD_Transmitter CPLD_Transmitter(
    .Clk(SysClk), 
	 .BckIn(BckIn), 
	 .LrckIn(LrckIn), 
	 .DataIn(DataIn[16]),
	 .StartFlag(RstN)
    );
    
    initial    // Clock process for clk
        begin
            #100;
            forever
            begin
                SysClk = 1'b0;
                #5 SysClk = 1'b1;
                #5;
            end
        end
		  
	initial    // Clock process for BckIn
        begin
            #100;
				BckIn = 1'b0;
						 #20 BckIn = 1'b1;
						 #20;
						 BckIn = 1'b0;
						 #20 BckIn = 1'b1;
						 #20;BckIn = 1'b0;
						 #2440;
            forever
            begin
					if(counterIn <= 6000)
						begin
							BckIn = 1'b0;
						 #20 BckIn = 1'b1;
						 #20;
						end
					else
						begin
							BckIn = 1'b0;
							#1280;
						end	
            end
        end
		  
	initial    // Clock process for LrckIn
        begin
            #100;
            forever
            begin
					if(counterIn <= 6000)
						begin
							 LrckIn = 1'b0;
							 #1280 LrckIn = 1'b1;
							 #1280;
						end	
					else
						begin
							LrckIn = 1'b0;
							#1280;
						end
            end
        end
		  
	initial    // Clock process for LrckIn
        begin
		      counterIn = 0;
            #100;
				#1280;
				#1280;
            forever
            begin
					counterIn = counterIn + 1;
					#1280;
					#1280;
            end
        end
	
	initial    // Clock process for BckIn
        begin
            #110;
            forever
            begin					
					DataIn = {DataIn[15:0], DataIn[15] ^ DataIn[2] ^ DataIn[1]};
					 #40 ;
            end
        end

    initial    // Clock process for clk
        begin
            RstN = 0;
            #2200;
            RstN = 1;
        end       
    
endmodule