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- Info: Start Nativelink Simulation process
- Info: NativeLink has detected Verilog design -- Verilog simulation models will be used
- ========= EDA Simulation Settings =====================
- Sim Mode : RTL
- Family : maxii
- Quartus root : d:/altera/13.1/quartus/bin64/
- Quartus sim root : d:/altera/13.1/quartus/eda/sim_lib
- Simulation Tool : modelsim
- Simulation Language : verilog
- Simulation Mode : GUI
- Sim Output File :
- Sim SDF file :
- Sim dir : simulation\modelsim
- =======================================================
- Info: Starting NativeLink simulation with ModelSim software
- Sourced NativeLink script d:/altera/13.1/quartus/common/tcl/internal/nativelink/modelsim.tcl
- Warning: File CPLD_Transmitter_run_msim_rtl_verilog.do already exists - backing up current file as CPLD_Transmitter_run_msim_rtl_verilog.do.bak11
- Info: Spawning ModelSim Simulation software
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