cpld/CPLD_Transmitter.qsf

# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, the Altera Quartus II License Agreement,
# the Altera MegaCore Function License Agreement, or other 
# applicable license agreement, including, without limitation, 
# that your use is for the sole purpose of programming logic 
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# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 14.0.0 Build 200 06/17/2014 SJ Full Version
# Date created = 05:19:43  September 28, 2023
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		CPLD_Transmitter_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name DEVICE EPM570T100C5
set_global_assignment -name TOP_LEVEL_ENTITY CPLD_Transmitter
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "05:19:43  SEPTEMBER 28, 2023"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH CPLD_Transmitter_tbb -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME CPLD_Transmitter_tbb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id CPLD_Transmitter_tbb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME CPLD_Transmitter_tbb -section_id CPLD_Transmitter_tbb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 us" -section_id CPLD_Transmitter_tbb
set_global_assignment -name EDA_TEST_BENCH_FILE CPLD_Transmitter_tbb.vt -section_id CPLD_Transmitter_tbb
set_global_assignment -name VERILOG_TEST_BENCH_FILE CPLD_Transmitter_tbb.vt
set_global_assignment -name VERILOG_FILE CPLD_Transmitter.v
set_global_assignment -name SOURCE_FILE db/CPLD_Transmitter.cmp.rdb
set_global_assignment -name QIP_FILE IP_FIFO.qip
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "D:\\modeltech64_2020.4\\quartus" -section_id eda_simulation
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_73 -to StartFlag
set_location_assignment PIN_67 -to LrckIn
set_location_assignment PIN_76 -to BckIn
set_location_assignment PIN_71 -to DataIn
set_location_assignment PIN_12 -to Clk
set_location_assignment PIN_18 -to LrckOut
set_location_assignment PIN_19 -to BckOut
set_location_assignment PIN_20 -to DataOut