cpld/CPLD_Transmitter - 副本 (4).v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/05/17 23:16:57
// Design Name: 
// Module Name: CounterTest
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module CPLD_Transmitter(
    Clk, BckIn, LrckIn, DataIn, 
	 BckOut, LrckOut, DataOut, StartFlag,
	 FifoWordOut0,FifoWordOut1,FifoWordOut2,FifoWordOut3,RegDataInOut,DinWenDelayOut
    );
    input Clk, BckIn, LrckIn, DataIn;
	 input StartFlag;
	 output BckOut, LrckOut, DataOut;
	 output FifoWordOut0,FifoWordOut1,FifoWordOut2,FifoWordOut3,RegDataInOut,DinWenDelayOut;
	
	 parameter ConstDinStateCounterFull = 16'd44000;
	 parameter ConstDinStateCounter = 16'd43998;
	 parameter ConstFifiReadOutterCounter = 16'd43999;
	 
	 ///// In Part
	 reg RegLrckIn = 0;
	 reg RegDataIn = 0;
	 reg PreRegLrckIn = 0;
	 reg PreRegDataIn = 0;
	 reg DinWen = 0;
	 reg DinWenDelay = 0;
	 reg [15:0] DinStateCounter = 0;
	 reg [1:0] DinState = 0;	 
	 reg [5:0] DinInnerCounter = 0;
	 reg [1:0] DinStateNeg = 0;
	 
	 ///// Out Part
	 reg [1:0] BckOutCounter = 0;
	 reg [5:0] LrckOutCounter = 0;
	 reg FifoRen = 0;
	 reg FifoRenPos = 0;	
	 reg DataOut = 0;
	 reg [6:0] InnerInputCounter=0;
	 reg [4:0] DoutReadCounter = 0;
	 reg [1:0] ReadState = 0;
	 reg [4:0] DoutReadCounterPos = 0;
	 reg [1:0] ReadStatePos = 0;
	 reg [31:0] FifoShifter = 0;
	 reg [15:0] FifiReadOutterCounter = 0;
//	 reg ReadStart = 0;
	 wire [5:0] FifoWord;
	 wire FifoEmp;
	 wire FifoReadOut;
    
	 assign BckOut = BckOutCounter[1];
	 assign LrckOut = LrckOutCounter[5];
	 
	 //测试端口
	 assign FifoWordOut0 = FifoWord[0];
	 assign FifoWordOut1 = FifoWord[1];
	 assign FifoWordOut2 = FifoWord[2];
	 assign FifoWordOut3 = FifoWord[3];
	 assign RegDataInOut = RegDataIn;
	 assign DinWenDelayOut = DinWenDelay;
	 
	 ///// In Part Logic
	 always@(posedge BckIn)
		begin
			if(StartFlag == 1'b0)
				begin
					PreRegLrckIn <= 1'b0;
					PreRegDataIn <= 1'b0;
				end
			else
				begin
					PreRegLrckIn <= LrckIn;
					PreRegDataIn <= DataIn;
				end
		end
		
	always@(negedge BckIn)
		begin
			if(StartFlag == 1'b0)
				begin
					RegLrckIn <= 1'b0;
					RegDataIn <= 1'b0;
				end
			else
				begin
					RegLrckIn <= PreRegLrckIn;
					RegDataIn <= PreRegDataIn;
				end
		end	
		
   always@(posedge BckIn)
		begin
			if(StartFlag == 1'b0)
				begin
					InnerInputCounter <= 7'd62;
				end
			else
				begin
					if((DinStateNeg==2'd2)||(DinStateNeg==2'd0))
						begin
							if(InnerInputCounter < 7'd62)
								begin
									InnerInputCounter <= InnerInputCounter + 7'd1;
								end
							else
								begin
									if( (RegLrckIn == 1'b1) && (LrckIn == 1'b0) )
										InnerInputCounter <= 7'd0;
								end
						end
					else
						InnerInputCounter <= 7'd62;
				end
		end	
	
	always@(posedge BckIn)
		begin
			if(StartFlag == 1'b0)
				begin
					DinInnerCounter <= 6'd0;
				end
			else
				begin
					if(DinStateNeg==2'd2)
						begin							
							if( (RegLrckIn == 1'b1) && (LrckIn == 1'b0) )
								DinInnerCounter <= 6'd0;
							else	
								DinInnerCounter <= DinInnerCounter + 5'd1;
						end
					else
						DinInnerCounter <= 6'd0;
				end
		end
		
	always@(negedge BckIn)
		begin
			if(StartFlag == 1'b0)
				begin
					DinWenDelay <= 5'd0;
				end
			else
				begin
					DinWenDelay <= DinWen;
				end
		end	
		
	always@(negedge BckIn)
		begin
			if(StartFlag == 1'b0)
				begin
					DinStateNeg <= 2'd0;
				end
			else
				begin
					DinStateNeg <= DinState;
				end
		end
		
    always@(posedge BckIn)
		begin
			if(StartFlag == 1'b0)
				begin
					DinState <= 2'd0;
				end
			else
				begin
					case(DinStateNeg)
						2'd0:
							begin
								if( (RegLrckIn == 1'b1) && (LrckIn == 1'b0) )
									begin
										DinState <= 2'd2;
									end
							end
						2'd1:
							begin
								if( (RegLrckIn == 1'b1) && (LrckIn == 1'b0) )
									begin
										DinState <= 2'd2;
									end
							end
						2'd2:
							begin
								if( (RegLrckIn == 1'b1) && (LrckIn == 1'b0) && ( DinStateCounter == ConstDinStateCounter ) )
									begin
										DinState <= 2'd3;
									end
							end			
						2'd3:
							begin
								if( DinStateCounter == ConstDinStateCounterFull )
									begin
										DinState <= 2'd1;
									end
							end
									
					endcase				
				end
		end		
	
	always@(posedge BckIn)
		begin
			if(StartFlag == 1'b0)
				begin
					DinStateCounter <= 16'd0;
				end
			else
				begin
					if(DinStateNeg == 2'd2 || DinStateNeg == 2'd3)
						begin
							if( (RegLrckIn == 1'b1) && (LrckIn == 1'b0) && (InnerInputCounter == 7'd62))
								begin
									DinStateCounter <= DinStateCounter + 16'd1;
								end
							else
								DinStateCounter <= DinStateCounter;
						end
					else
						DinStateCounter <= 16'd0;
				end
		end
		
	always@(posedge BckIn)
		begin
			if(StartFlag == 1'b0)
				begin
					DinWen <= 1'd0;
				end
			else
				begin
					case(DinStateNeg)
						2'd0:
							begin
								if( (RegLrckIn == 1'b1) && (LrckIn == 1'b0) )
									begin
										DinWen <= 1'd1;
									end
							end
						2'd1:
							begin
								if( (RegLrckIn == 1'b1) && (LrckIn == 1'b0) )
									begin
										DinWen <= 1'd1;
									end
							end
						2'd2:
							begin
								if( (DinStateCounter == ConstDinStateCounter)  || (DinInnerCounter == 5'd24))
									begin
										DinWen <= 1'd0;
									end
								else if((DinStateCounter <= ConstDinStateCounter) && ( (RegLrckIn == 1'b1) && (LrckIn == 1'b0) ) )
										DinWen <= 1'd1;
							end
					endcase	
				end
		end
		

	IP_FIFO IP_FIFO(
	.aclr(!StartFlag),
	.data(RegDataIn),
	.rdclk(BckOut),
	.rdreq(FifoRen),
	.wrclk(BckIn),
	.wrreq(DinWenDelay),
	.q(FifoReadOut),
//	.rdempty(FifoEmp),
	.rdusedw(FifoWord)
	);		
	
	///// Out Part Logic	
	
	always@(posedge Clk)
		begin
			BckOutCounter <= BckOutCounter + 2'd1;
		end	

	always@(negedge BckOut)
		begin
			LrckOutCounter <= LrckOutCounter + 6'd1;
		end
		
	always@(posedge BckOut)
		begin
			DoutReadCounterPos <= DoutReadCounter;
		end	
		
	always@(negedge BckOut)
		begin
			if((LrckOutCounter==6'd63) || (LrckOutCounter==6'd31))
				DoutReadCounter <= 5'd0;
			else
				DoutReadCounter <= DoutReadCounterPos + 5'd1;
		end
		
	always@(posedge BckOut)
		begin
			FifoRenPos <= FifoRen;
		end			
		
	always@(negedge BckOut)
		begin
			if( (LrckOutCounter == 6'd62) && (FifoWord >= 6'd6) && (ReadStatePos == 2'd0) )
				FifoRen <= 1'd1;
			else if( (LrckOutCounter == 6'd62) && (ReadStatePos == 2'd1) )	
				FifoRen <= 1'd1;
			else if( (LrckOutCounter == 6'd23) && (FifoRenPos == 1'd1)  )	// && (ReadStatePos == 2'd1)
				FifoRen <= 1'd0;		
		end
		
	always@(posedge BckOut)
		begin
			if(StartFlag == 1'b0)
				begin
					ReadStatePos <= 2'd0;
				end
			else
				begin
					ReadStatePos <= ReadState;
				end
		end
	
	always@(posedge BckOut)
		begin
			if(StartFlag == 1'b0)
				begin
					FifiReadOutterCounter <= 16'd0;
				end
			else
				begin
					if(ReadStatePos == 1'b0)
						FifiReadOutterCounter <= 16'd0;
					else
						begin
							if( (LrckOutCounter == 6'd62) && (FifiReadOutterCounter < ConstFifiReadOutterCounter))
								FifiReadOutterCounter <= FifiReadOutterCounter + 16'd1;
							else
								FifiReadOutterCounter <= FifiReadOutterCounter;
						end
				end
		end	
		
		
	always@(negedge BckOut)
		begin
			if(StartFlag == 1'b0)
				begin
					ReadState <= 2'd0;
				end
			begin	
				if( (LrckOutCounter == 6'd62) && (FifoWord >= 6'd6) )
					ReadState <= 2'd1;
				else if( (FifoWord <= 6'd1) && (ReadState == 2'd1) && (FifiReadOutterCounter == ConstFifiReadOutterCounter )	)
					ReadState <= 2'd0;
			end
		end
		
	always@(negedge BckOut)
		begin
			FifoShifter <= {FifoShifter[29:0], DataOut};
		end
	
	always@(negedge BckOut)
		begin
			if(ReadStatePos == 1'b0)
				DataOut <= 1'b0;
			else
				begin
					if(FifoRenPos == 1'b1)
						DataOut <= FifoReadOut;
					else
						DataOut <= FifoShifter[30];
				end
		end	
	
endmodule